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The article focuses on the significance of slow computing to control transistor switching in microprocessors resulting in lowering the voltage and manage energy consumption. Topics discussed include use of complementary metal-oxide semiconductor (CMOS) to operate at a lower voltage, use of registers-logic gates to hold data values that retain their contents when the supply voltage is removed, and aspects of double-gate transistor built onto a silicon-on-insulator in microprocessors.

Behavioural synthesis is the process of automatically translating an abstract specification to physical realisation - silicon. The endpoints of this process are accelerating apart (behavioural descriptions become more abstract, DSM silicon becomes less willing to behave as Boolean circuits) but there is still work outstanding in the middle ground. Recursion allows the elegant expression of complicated systems, and is supported by many languages (software and hardware). The electronic design automation (EDA) tool designers' task is to support the semantics of a language (both simulation and synthesis). Although recursive descriptions can always be re-cast into non-recursive iterative forms, if a language supports a construct, a user should be able to utilise it (the authors are not offering any opinion on the relative wisdom of using recursion or iteration). The authors describe the problems/solutions of supporting the semantics of recursion (single/multiple, direct/ arbitrarily indirect) in synthesis. The hardware synthesised can be smaller and faster than that obtained by reformulating the description. It is dangerous, to conclude too much from this - recursion requires a stack and a heap (plus managers). In software, these are taken for granted ('free' resources that do not feature in footprint metrics); in hardware, every resource needed must be explicitly created. [ABSTRACT FROM AUTHOR]

Today's multi-million digital integrated circuit design highly depends on the quality of the standard cell library. In this study, an all-digital reconfigurable-array-based test structure is presented to test the quality (i.e. functionality and performance) of all types of logic gates in the standard cell library using the reconfigurable array of gate delay measurement cell. The gate delay is estimated using the least squares method with measured reconfigurable ring oscillator's (RO) period/frequency. As the least squares method averages out the random noise in the measured RO period, measured gate delay is estimated accurately. The reconfigurable-array structure can easily isolate a faulty standard cell from a non-faulty standard cell. The test structure is area efficient with a saving of 1.6× and 2× area compared with the normal RO-based delay measurement in 180 nm and 65 nm technology node, respectively. A subset of standard cells is tested using this reconfigurable-array structure. A test chip has been fabricated in an industrial 180 nm technology node to study the feasibility of the approach. The measured results from 20 chips are reported to show the amount of within-die and die-to-die variation. [ABSTRACT FROM AUTHOR]

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The simulation results represent protocol accuracy and show 57% throughput improvement on average compared with the scheduling-based methodology. The protocol also shows area reduction for the majority of simulated systems. [ABSTRACT FROM AUTHOR]

Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value -1(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2n+1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum. [ABSTRACT FROM AUTHOR]

Hardware designs that can support multiple standards are required for versatile media players. The study proposes a unified inverse transform architecture that can be efficiently used in Moving Picture Expert Group and ITU International Telecommunication Standardisation Sector (ITU-T) H.264/advanced video coding (AVC), Microsoft video codec 1 (VC-1) and Chinese Audio Video Coding Standard (AVS) decoders. For H.264/AVC 8-, 4- and 2-point inverse transforms, the computational complexity in the proposed architecture is similar to that defined in the H.264/AVC standard. By using the symmetry of the transform matrices, the matrix product operations of the inverse transforms in VC-1 and AVS are efficiently decomposed to use only shifters, adders and subtractors. All the computations are verified and designed using a hardware unit to achieve a low-cost hardware kernel. The proposed multiple-transform architecture contains fast 1-D transforms and rounding operations for the computation of H.264/AVC, VC-1 and AVS 8- and 4-point inverse transforms. Simulation results show that the total number of gates for the proposed architecture is 8983, which is much lower than that required for architectures without hardware sharing. Compared with individual designs, the proposed shared architecture reduces the number of logic gates by a factor of two with a penalty of 20% in data throughput. [ABSTRACT FROM AUTHOR]

Low-power consumption and stability in static random access memories (SRAMs) is essential for embedded applications. This study presents a novel design flow for power minimisation of nano-complementary metal-oxide semiconductor SRAMs, while maintaining stability. A 32 nm high-κ/metal-gate SRAM has been used as an example circuit. The baseline circuit is subjected to power minimisation using a dual-threshold voltage assignment based on novel combined design of experiments and integer linear programming (DOE-ILP) approach. However, this leads to a 15% reduction in the static noise margin (SNM) of the cell. The conjugate gradient optimisation overcomes this SNM degradation, while reducing the power consumption. The final SRAM design shows 86% reduction in power consumption (including leakage) and 8% increase in the SNM compared with the baseline design. The variability analysis of the optimised cell is performed by considering the effect of 12 parameters. SRAM arrays of different sizes are constructed to demonstrate the feasibility of the proposed SRAM cell. To the best of the authors' knowledge, this is the first study which makes use of DOE-ILP and conjugate gradient method for simultaneous stability and power optimisation in high-κ/metal-gate SRAM circuits. [ABSTRACT FROM AUTHOR]

When a logic block is embedded in a larger design, the input sequences applicable to it may be constrained by other logic blocks in the design. This has an impact on what would constitute overtesting of the logic block by scan-based tests. This study defines functional broadside tests that avoid overtesting for an embedded block based on functional broadside tests for the larger design. The definition is constructive and results in a procedure for generating the tests. This study compares these tests with ones generated for the logic block as a stand-alone circuit. The results demonstrate that it is important to consider in the discussion of overtesting the extent to which the functionality of an embedded logic block is utilised as a part of the design. Under certain conditions it is possible to apply to the logic block functional broadside tests that were generated for it as a stand-alone circuit in order to maximise the fault coverage without overtesting, and reduce the computational complexity of test generation. [ABSTRACT FROM AUTHOR]

A new design flow for security is presented. Cryptographic circuit specifications are first refined and then mapped to a secure power-balanced library consisting of novel mixed 1-of-2 and 1-of-4 components based on N-nary logic. Logic optimisation tools are then applied to generate secure synchronous circuits for layout generation. The circuits generated are more efficient than balanced circuits generated by alternative techniques. A new method is presented for evaluating the security of such circuits. A security metric is introduced, which is based on the common selection function that is widely used in differential power analysis (DPA) attacks and a correlation measure similar to the one used in correlation power analysis (CPA) attacks. The metric enables the construction of a library of robust cryptograhic components including S-boxes that are more resistant to attack. [ABSTRACT FROM AUTHOR]

In a broadside test, a scan-in operation is followed by two functional clock cycles where primary input vectors, denoted by v0 and v1, are applied. Because of tester limitations that prevent the primary input vectors from being changed at speed, broadside tests are computed under the constraint where v0=v1. This results in a loss of delay fault coverage. This study develops a fast procedure for identifying transition faults that are undetectable by broadside tests under the constraint v0=v1. Faults that are undetectable because of this constraint are undetectable because of tester limitations and not because of the logic in the circuit. These faults may be able to affect the circuit during functional operation, when the primary input vectors are unconstrained. In this case the faults are important to detect. A fast procedure for identifying undetectable transition faults under the constraint v0=v1 provides a quantitative measure of the effect of this constraint on the achievable fault coverage without performing test generation. If it turns out that the effect on fault coverage is unacceptable, other solutions may be used without first performing test generation. [ABSTRACT FROM AUTHOR]

A DC∼10.5 GHz complimentary metal oxide semiconductor (CMOS) distributed amplifier (DA) with flat and low noise figure (NF), flat and high power gain (S21) and small group delay (GD) variation for ultra-wideband (UWB) pulse radio systems using standard 0.18 µm CMOS technology is demonstrated. Flat and low NF was achieved by adopting the proposed resistor capacitor (RC) terminal network with 140 Ω terminal resistance over the frequency band of interest (instead of the traditional 50 Ω terminal resistance or the recently proposed resistor inductor (RL) terminal network) for the gate transmission line. Besides, flat and high S21 was achieved by using cascoded transistors as the gain cell. Over the DC∼10.5 GHz band, the DA consumed 29.16 mW and achieved flat and high |S21| of 10.5±1.4 dB, flat and low NF of 3.2±0.3 dB and excellent phase linearity (the GD variation was only ±13.8 ps), one of the best NF and phase linearity results ever reported for a CMOS DA or wideband low-noise amplifier (LNA) with bandwidth greater than 7.5 GHz. [ABSTRACT FROM AUTHOR]

Power consumption is the most important issue in circuit design nowadays, and clock gating is the most widely used technique to reduce the dynamic power at register transfer level. The traditional clock gating style using an XOR gate to generate a gated clock was proposed but has not been well studied. It can be extended to multiple flip-flops easily but the power performance is not optimal. In this study, the authors propose a fine-grained activity-driven optimised bus-specific-clock-gating for ultra-low-power smart spaces applications, which can selectively choose qualified flip-flops to be gated based on their output switching activities to optimise the power. This technique has been experimented on ISCAS'89 benchmark circuits, and average power can be reduced by 19.21%. [ABSTRACT FROM AUTHOR]

In this study, a new approach using a multi-objective genetic algorithm (MOGA) is proposed to determine the optimal state assignment with less area and power dissipations for completely and incompletely specified sequential circuits. The goal is to find the best assignments which reduce the component count and switching activity. The MOGA employs a Pareto ranking scheme and produces a set of state assignments, which are optimal in both objectives. The ESPRESSO tool is used to optimise the combinational parts of the sequential circuits. Experimental results are given using a personal computer with an Intel CPU of 2.4 GHz and 2 GB RAM. The algorithm is implemented using C++ and fully tested with benchmark examples. The experimental results show that saving in components and switching activity are achieved in most of the benchmarks tested compared with recent published research. [ABSTRACT FROM AUTHOR]

Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. As there are no external timing references, data must be encoded within an unordered (DI) encoding and the outputs of functions must indicate to the environment that transitions on inputs and internal signals have taken place. Mapping large function blocks into cell-libraries is extremely difficult as decomposing gates introduces new signals which may violate indication. This study presents a novel method for implementing any m-of-n-encoded function block using 'bounded gates', where any gate may be decomposed without violating indication. This is achieved by successively decomposing the input encoding into smaller unordered codes. The study presents algorithms to determine and quantify potential re-encodings. An exact branch and bound approach to the solution is shown, but the complexity of determining unordered encodings restricts the size of function blocks that may be decomposed. To overcome this problem, an approach has been proposed that uses algebraic extraction techniques to efficiently determine and quantify potential encodings. The results of the synthesis procedures are demonstrated on a range of combinational function blocks. [ABSTRACT FROM AUTHOR]

Magnetic quantum cellular automata (MQCA) is a nano-scale computational paradigm that utilises magnetic dipolar interaction and coupling to propagate and process binary information. Characteristics of signal propagation in MQCA circuits with pipelined clocking signals are evaluated for the purposes of fast and reliable logic operation. These circuits are simulated via the Landau-Lifshitz-Gilbert equations and object-oriented micro-magnetic framework tool. It is found that signal propagations in the thin nanomagnet circuits are blocked significantly as the damping parameter is increased; however, their switching times decrease as the damping parameter increases. Switching speeds of MQCA structures are improved as the thickness and damping parameter are increased. The results also show that the majority logic gate performs a complete reliable operation for nanomagnet thicker than about 20 nm, whereas for interconnect wire, thickness ranging from only about 20 to 25 nm introduces a successful operation. [ABSTRACT FROM AUTHOR]

The review focuses on semiconductor nanoparticles and hybrid materials obtained by immobilisation of various molecular species on nanoparticulate semiconductors. These materials constitute unique systems combining collective properties of solids with structural diversity of molecules which show distinctive photoelectrochemical properties. Theoretical models of electronic interactions between molecules and semiconductor surfaces have been presented. Additionally, the review summarises the idea of small particles that can work as electronic devices. These devices are able to sense the environment and communicate with other devices and with the user. The devices are based on surface modified wide-band gap semiconductors and the photoelectrochemical photocurrent switching effect. This effect has created a new platform for novel chemical switches, logic gates and other information processing devices. The mechanism of photocurrent switching is discussed with respect to the type of surface complex-support interaction. Photoelectrochemical properties of multicomponent photoelectrodes based on wide band gap nanocrystaline semiconductors modified with various molecules were investigated. The review presents some examples of hybrid materials working as logic devices, including reconfigurable ones and simple arithmetic systems together with mechanistic problems related to nanoscale information processing. [ABSTRACT FROM AUTHOR]

Elementary blocks, performing logic operations, are the building elements for more complex subsystems implementing all-optical digital processing. They can potentially enable next generation optical networks and optical computing, overcoming the limitations of the electronics bandwidth, also guaranteeing scalability, transparency, easy reconfigurability and modularity. Finally, integrated technologies can reduce power consumption, footprint and cost. [ABSTRACT FROM AUTHOR]

In this study, the authors propose a novel optical waveguide consisting of arrays of silicon nanowires (SiNWs) in close proximity for applications to all-optical logic operations. The logic operations are based on two non-linear phenomena, stimulated Raman scattering (SRS) and free carrier absorption (FCA). Since, the SRS coefficient is increased in the nanowire regime, the performance of the optical logic gates in terms of optical power required can be improved by a factor of at least 7 using our proposed waveguides. The advantage of the proposed waveguide is that it allows for increased photon-carrier interactions while keeping the optical confinement factor high even when the individual nanowire diameters are less than 100 nm. We analyse the waveguides using the finite-difference time domain method and show that the radiation loss is less than 0.034 cm-1. Further, the waveguide allows for optical guidance even when the nanowires are randomly arranged. We also show a maskless etch method to create SiNWs with dimensions required to create our proposed waveguide structure. [ABSTRACT FROM AUTHOR]

The authors describe how a simple way to split input operands allows for fast VLSI implementations of subquadratic GF(2)[x] Karatsuba–Ofman multipliers. The theoretical XOR gate delay of the resulting multipliers is reduced significantly. For example, it is reduced by about 33 and 25% for n = 2t and n = 3t (t > 1), respectively. To the best of our knowledge, this parameter has never been improved since the original Karatsuba–Ofman algorithm was first used to design GF(2n) multipliers in 1990. [ABSTRACT FROM AUTHOR]

A low-voltage 1.2-V, 10-bit, 60–360 MS/s six channels time-interleaved reset-opamp pipelined ADC is designed and implemented in a 0.18-µm CMOS (VTHN/VTHP=0.63 V/-0.65 V for mid-supply floating switches). Without using on-chip high-voltage and low-VT options, the proposed ADC employs low-voltage resistive-demultiplexing techniques, low-voltage gain-and-offset compensation, feedback current biasing to reduce the sensitivity of the bias current over process variations and current-mode sub-ADCs with static current sharing for a low-voltage time-interleaved implementation. Speed options of 60–360 MS/s are available with scalable power and they can be obtained by automatic selection of the number of time-interleaved channels. The chip measurement results show that the ADC exhibits a differential non-linearity (DNL)/integral non-linearity (INL) better than 0.9/1.2 LSB and a peak SNDR above 54 dB, for all speed options, while consuming 85 mW at 60 MS/s and 426 mW at 360 MS/s. The active die area is 13.2 mm2. [ABSTRACT FROM AUTHOR]

Most current audio coding standards use the modified discrete cosine transform (MDCT) to transform an audio sequence from the time domain into the frequency domain. Existing architectures for MDCT use a lookup table to store cosine values in read-only memory (ROM). For MPEG-2/4 AAC, the memory space taken up by the required lookup table makes the circuit implementation inflexible and large because of the long window length. Therefore this study proposes a memory-free architecture for MDCT without a lookup table. The proposed architecture adopts the arithmetic circuit module to calculate the cosine function based on the Taylor and Maclaurin series approximations and makes use of the symmetric and periodic identities of trigonometric functions to reduce circuit complexity. 0.18 µm TSMC cell library technology is used to synthesise the proposed architecture, which requires about 9213 gates with a maximum operation frequency of 100 MHz. The proposed architecture, which has a flexible window length to perform MDCT, can be implemented in an area smaller than that of ROM-based architectures. [ABSTRACT FROM AUTHOR]

There have been several strategies proposed to realise adiabatic circuits. Most of them require a clock signal and also its complement form. In this investigation, the authors we propose a family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs. A mathematical expression has been developed to explain the energy dissipation in our adiabatic inverter circuit. Measurements of energy drawn, recovered and dissipated have been carried out through simulation and, they are the same as obtained from the theoretical expression. In the proposed circuit, the input and output logic levels are approximately the same and can be used for building cascaded logic circuits. The energy saving in this family is to the tune of 50% compared with CMOS circuits constructed with similar circuit parameters, up to 250 MHZ. The authors have described the proposed inverter, NAND gates, NOR gates, adder circuits and JK flip-flop along with their simulation results. [ABSTRACT FROM AUTHOR]

Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of ∼115 ps and an energy dissipation of ∼33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower. [ABSTRACT FROM AUTHOR]

The adjoint circuit of a multiple output second-generation current conveyor (MOCCII) is investigated. It is found that the adjoint circuit of MOCCII is an multi-input differential current conveyor (MIDCC). A CMOS realisation of the MIDCC with three plus-type input terminals and two minus-type input terminals is described. As an example of applying the MIDCC, the transforming of a current-mode filter using MOCCIIs to its adjoint voltage-mode filter using MIDCCs is discussed. [ABSTRACT FROM AUTHOR]

The linearity of an efficient polar transmitter architecture, with a 1 bit oversampled delta–sigma (ΔΣ) modulating the envelope signal, depends, to a high degree, on low-pass envelope filtering. This filter is compulsory to attenuate the ΔΣ quantisation noise. A high cut-off frequency results in more noise being included. In contrast, using a filter with a low cut-off frequency results in attenuation of the information content of the envelope signal. Either way, the result is unwanted spectral regrowth. By pre-emphasising the envelope signal, the filter's attenuation of the information is mitigated. The pre-emphasis is implemented by a digital pseudo-derivative high-pass filter, with inverse magnitude characteristics of the analogue low-pass filter, within a limited interest band. Consequently, the low-pass filter can be designed with a lower cut-off frequency to attenuate more of the ΔΣ modulator noise, and the modulator can switch at lower frequencies. With this technique, the WLAN output spectrum, at the critical 30 MHz offset corner frequency, is improved by 12.5 dB, considering a second order ΔΣ sampling at 1.28 GHz. The technique was verified with an experimental setup and the behaviour agrees well with simulations. [ABSTRACT FROM AUTHOR]

The silicon-on-insulator (SOI) CMOS technology is one of the best candidates for high-temperature applications due to its low leakage current, steep subthreshold slope, absence of latch-up phenomenon and temperature-resistant threshold voltage. However, the most critical elements for high temperature applications are transmission lines, especially thin-film microstrip lines. In the paper, the impact of high-temperature operation on the RF performance of some SOI circuits is analysed up to 250°C. [ABSTRACT FROM AUTHOR]

A general design approach to design polymorphic circuits with polymorphic gates is proposed. These polymorphic circuits can adaptively adjust their functionalities with the changes of the electrical characteristics of components induced by the change of environment. The single function circuits that can work correctly and maintain their functionalities in different environments can be regarded as a special kind of polymorphic circuits. The general design approach for these circuits is proposed, and based on this approach, the general design approach to designing polymorphic circuits is also proposed. It is proved that a polymorphic circuit with any two different functions in two different environments can be implemented with a complete polymorphic gate set, and a definition on the gate set is given and the completeness is also discussed. Finally, these general design approaches are analysed and some experiments are performed to demonstrate their efficiency. [ABSTRACT FROM AUTHOR]

A diagnostic tool for bridging faults combining three different data sources is presented. The first data source is a set of IDDQ measurements used to identify the most probable fault type. The second source is a list of parasitic capacitances extracted from layout and used to create a list of realistic potential bridging fault sites. The third source is logical faults detected at the primary outputs (including scan flip flops), used to limit the number of suspected gates. The combination of these data significantly reduces the number of potential fault sites to consider in the diagnosis process. Simulation results confirm that the number of potential bridging fault sites is reduced from O(N2) to less than O(N), where N is the number of nodes in the circuit. The tool therefore converges quickly towards the solution while using less resources. A new technique is also introduced to estimate the additional delay caused by the diagnosed bridging fault based on the diagnostic results. Performing this estimation allows us to confirm the previous diagnosis results. [ABSTRACT FROM AUTHOR]

Hold-time violation is a common cause of failure at scan chains. A robust new paradigm for diagnosing such failures is presented. As compared to previous methods, the main advantage of this is the ability to tolerate non-ideal conditions, for example, under the presence of certain core logic faults or for those faults that manifest themselves intermittently. The diagnosis problem is first formulated as a ‘delay insertion process’. Upon this formulation, two algorithms – a ‘greedy’ algorithm and a so-called ‘best-alignment-based’ algorithm – is proposed. Experimental results on a number of practical designs and ISCAS'89 benchmark circuits are presented to demonstrate its effectiveness. [ABSTRACT FROM AUTHOR]

The authors present a new fully differential current-mode third-order Butterworth very high frequency Gm-C filter using current-mode linear transformation (CMLT) techniques. The systematic design method and procedure are developed to realise CMLT Gm-C filters efficiently. A third-order Butterworth lowpass filter with 200 MHz cutoff frequency, embedded bandgap reference and bias circuit is implemented in a TSMC 0.18 μm 1P6M process. The total harmonic distortion of the proposed current-mode filter is -46.5 dB at 200 MHz with input signal 0.4 mA. Power dissipation is 16.77 mW under 1.8 V supply voltage. Its core area occupies 0.163×0.186 mm2. Both post-layout simulation and experimental results confirm the theoretical analysis. The proposed circuits can be extended to high-order Chebychev and elliptic filters. [ABSTRACT FROM AUTHOR]

Dynamic CMOS logic styles are widely used in high-performance systems due mainly to their speed. However they have lower noise-tolerance than their static CMOS counterparts. To overcome this disadvantage a new noise-tolerant circuit technique, suitable for precharge-evaluate dynamic circuits, is presented. The technique is suitable for TSPC and domino gates. Comparisons with previously reported noise-tolerant dynamic circuit techniques are presented. Simulation results on TSPC and domino gates show that the proposed technique improves the noise tolerance of conventional dynamic gates with reduced performance overhead. The feasibility of this new technique is demonstrated by means of a pipelined 0.35 μm CMOS carry look-ahead full adder. Experimental results show an increased noise tolerance of up to three times over standard CMOS logic. [ABSTRACT FROM AUTHOR]

The paper presents a complete portfolio of RF and baseband components by adopting RFCMOS technology for single-chip systems. Using optimised CMOS topology and deep n-well, the performance relates to the ft of 60 GHz and fmax of 53 GHz at 10 mA, an ft of 70 GHz and fmax of 58 GHz at maximum-transconductance bias, and a minimum noise figure of 1.5 dB without ground-shielded signal pad. High quality-factor inductors are obtained using thick copper interconnects; the measurement result demonstrates the corresponding quality factor of 18 at 1.7 nH. The MIM capacitors, as well as accumulation-mode MOS and junction varactors are also optimised for improving quality factor. For the purpose of eliminating inter-block coupling noise penetrating through the substrate, a deep n-well isolation and a p-well guard-ring have been adopted to suppress the substrate noise by 25 dB and 10 dB, respectively. [ABSTRACT FROM AUTHOR]

The load–store queue (LSQ) of modern superscalar processors is a critical and non-scalable component responsible for keeping the order of memory operations. As new architectures become more aggressive, the number of in-flight memory instructions increases, and the LSQ must satisfy higher capacity requirements. An efficient LSQ state filtering mechanism based on Bloom filtering is proposed, which, in conjunction with a dynamic or profiling-based predictor, provides significant energy reduction (up to 55% in the LSQ and 4% in the whole processor), and only incurs a small performance loss. [ABSTRACT FROM AUTHOR]

It is a well-known fact in logic design that synthesis of some special classes of Boolean functions is often easier than the synthesis of a general unrestricted specification. In reversible logic, well-scaled synthesis methods with a reasonably small cost of the associated implementation have been found for only a few classes of functions. This includes synthesis of multiple-output symmetric and reversible linear functions. The author presents an efficient reversible/quantum synthesis method for the class of multiple-output symmetric functions. The method is purely theoretical, therefore its scaling on functions with a large number of inputs/outputs requires minimal resources. The author calculates garbage, i.e. the number of outputs that are not required by the function specification, the number of reversible gates, and the quantum cost of the presented implementations. The proposed approach is then applied to the synthesis of benchmark functions. Comparison of the designs to the previously reported implementations is favourable. [ABSTRACT FROM AUTHOR]

A novel algorithm for full-addition of two signed, higher-radix numbers is proposed and implemented by combining multi-valued logic min, max, literal and cyclic operators. Owing to disjoint terms involved, multi-valued logic min and max operators are replaced with ordinary transmission operation and sum, respectively. A multi-valued logic cyclic gate is designed by using a current-mode threshold circuit while the literal is realised by only voltage-mode switching circuits. The threshold circuit employed within the cyclic gate exhibits improved dynamic behaviour compared to its previous counterparts employing voltage-mode binary logic switching circuits. It also allows much higher radices compared to previous current-mode threshold circuits owing to its superior mismatch properties. Thus, the cyclic gate achieves a superior performance compared to its predecessors. As a direct extension to cyclic operation in radix-8, a resultant single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are designed and their performance compared. It is shown that the developed signed addition algorithm can be realised by using the proposed full-adder. Finally, the algorithm is also exploited for a multi-digit case. Simulation results demonstrate that proposed architectures can be used in high-performance arithmetic units. [ABSTRACT FROM AUTHOR]

An efficient way to obtain finite-state machines (FSMs) with low-power consumption is to partition the machine into two or more sub-FSMs and then use dynamic power management where all sub-FSMs not active are shut down, with the effect of reducing dynamic power dissipation. Thus, FSM partitioning algorithms and register-transfer-level power estimation functions are the main focus of the paper as these are key issues in the design of a computer-aided design tool for synthesis of low-power partitioned FSMs. An implementation architecture is targeted, which is based on both synchronous and asynchronous state memory elements that enable larger power reductions than fully synchronous architectures do. Power reductions of up to 77% have been achieved at a cost of an 18% increase in area. [ABSTRACT FROM AUTHOR]

A low-power and low-noise analogue multiplier operating with 1.5 V supply voltage is presented. The core structure consists of only six transistors and brings in the benefits in terms of linearity, power consumption and noise performance. Some design considerations are also provided. The extensive experiments with SPICE simulation show that this new structure is particularly attractive for low-power and low-noise applications in comparison with other previously reported structures. [ABSTRACT FROM AUTHOR]

The high leakage current in the nanometre regime is becoming a significant proportion of power dissipation in CMOS circuits as threshold voltage, channel length and gate oxide thickness are scaled. Consequently, the identification and estimation of different leakage currents are very important in designing low power circuits. In the paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modelling of the different leakage currents in nanoscaled bulk CMOS devices is demonstrated. Different leakage currents are modelled based on the device geometry, 2-D doping profile and operating temperature. A circuit level model of subthreshold, junction band-to-band tunnelling (BTBT) and gate leakage is described. The presented model includes the impact of quantum mechanical behaviour of substrate electrons on the circuit leakage. Using the compact current model, a transistor has been modelled as a sum of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25 nm effective length) at room and elevated temperatures. [ABSTRACT FROM AUTHOR]

Introduces an area-efficient current-mode comparator, which is based on modifications of the conventional complementary metal oxide semiconductor current comparator. Threshold current level; Use of the current-mode multiple-valued logic (CMMVL) approach; Improvement in power-delay product.

Investigates a novel imbalanced phase-switching technique for high-speed prescaler design. Use of 1/4 duty cycle phases to increase the delay budget in dual-modulus control; Improvement in the performance of the prescaler in terms of operating frequency and power consumption; Use of the Chartered 0.18 micron complementary metal oxide semiconductor process.

Discusses the importance of reusable verification components in combination with other techniques to provide a way of stressing the system to reveal bugs other approaches would not find. Significance of building reusable devices for verification to system designs; Devices that provides a reusable way of testing devices with a common functionality or common protocol; Effort of Infineon Technologies to build reusable verification components in the language e that exploit random testing techniques.

Presents a heuristic algorithm for three-level combinational logic optimization. Use of programmable logic arrays; Classical decomposition theory; Application of output phase optimization to the logic expander.

Investigates energy-efficient design for self-timed circuits. Use of null convention logic to construct speed-independent self-timed circuits; Cost of signal-to-noise ratio; Novel supply voltage scheme for error-free computation; Analysis of the energy-quality trade-off for error-tolerable computations in speed-independent circuits.

The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. A test generation method is proposed for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault-dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. Structural analysis obtains a superset of the maximally dominating fault set. A method is proposed for determining exact sets of maximally dominating faults. New types of n-detection test sets are based on the approximate and exact sets of maximally dominating faults. The test sets are called (n, n2)-detection test sets and (n, n2, n3)-detection test sets. Experimental results demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits. [ABSTRACT FROM AUTHOR]

A logic family called no-race charge-recycling complementary pass transistor logic (NCRCPL) is proposed. The use of a new regenerator in NCRCPL leads to a complete elimination of the controller in the circuit hence reducing the number of transistors and power consumption. It has an additional benefit of reduced sensitivity to signal skew. The proposed logic family in its modular structure also has a better performance than previous modular structures based on charge recycling. Furthermore, a latch structure called dual-rail isolated latch which can be used for pipelining NCRCPL has been proposed. The new latch had a much better performance compared with previous static latch structures. To enhance the power efficiency of the pipeline configuration an event-detector circuit is proposed that may reduce the power consumption by up to 50% compared with previous pipeline configurations. To assess the performance improvements of the logic structures of this work compared with other charge recycling logic structures, logic gates and ripple carry adders are studied. [ABSTRACT FROM AUTHOR]

Behavioral synthesis is the process whereby the description of a system behavior is automatically translated into a physical implementation of that system. An essential prerequisite of this process is a language in which to express the design. Traditionally, hardware description languages (HDLs) are used for this, but there is currently much interest in the idea of coercing conventional software languages to do the same job (SystemC is the most prominent example of this). The goal of the research described is to increase the synthesizable description space to support the description of systems utilizing dynamic allocation. VHDL supports the concepts of dynamic allocation, and is used as the entry language for the system, although without loss of validity SystemC could have been used. How the structures conventionally associated with dynamic description are implemented and supported is described together with a heap management subsystem that is both space and speed-efficient and which communicates with the user's design via an automatically generated interface. [ABSTRACT FROM AUTHOR]

Various representations of logic functions are frequently used in development of computer-aided design tools for VLSI digital circuits. Selected different compact representations of logic functions and their spectra are presented for the first time in lossless compression of grey-scale images. After coding of intensities, a prediction process is performed followed by the mapping of prediction residuals that are split into bit-planes to which the compression technique is applied. The planes can be coded as uncompressed or compressed using variable block-size segmentation and coding. The coding and compression schemes used include various compact representations of logic functions such as: minterm coding, co-ordinate data coding, discrete multiple-valued input binary functions, basic Walsh, triangular, Reed­Muller weights and spectra and the reference row technique. Experimental results indicate that the technique is efficient when compared with other methods. [ABSTRACT FROM AUTHOR]

Presents a method for improving the phase noise performance of a CMOS quadrature logic circuit oscillator through parasitic compensation. Paraistic resistance in the inductor; Impedance of the parallel LC resonator; On-chip spiral inductor model.

Describes a CMOS voltage reference design that uses the temperature dependence of NMOS and PMOS threshold voltages to form a temperature-insensitive reference. Circuit architecture; Fabrication of a test chip using a CMOS process; Supply voltage sensitivity.

Discusses the reliability problem of soft errors affecting computer memory. Impact of chip set errors on computer functions; Role of cosmic neutrons in soft errors; Susceptibility of logic circuits to soft errors; Possibility of soft failures in field programmable gate array; Efforts of computer companies to address the problem.