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For mission critical jobs in distributed computing, a network with a low packet loss rate and no failures is required. The multiple paths method has been studied as a means to achieve dependable communication with tolerable failures. It recovers from failures on a network using the same packet on another path. Since the speed of a long-distance network becomes faster, dependable communication that tolerates network latency becomes more important. We built a prototype system of a multiple paths method supporting Gigabit Ethernet speed using GtrcNET-1, a gigabit network testbed. We evaluated it and confirmed that it can continuously communicate even if a path fails, and it achieved a packet loss rate as low as the product of packet loss rates on both paths. © 2007 Wiley Periodicals, Inc. Syst Comp Jpn, 38(12): 46–54, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/scj.20807 [ABSTRACT FROM AUTHOR]

To analyze cell to cell interaction effects on cell differentiation, we developed a new triple staining method for double in situ hybridization with cell lineage tracing in whole-mount Xenopus embryos. The method provides high color contrast views, and also enabled us to examine inside the embryos. Wild-type embryos whose blastomere(s) had been injected with a cell lineage tracer were cultured, fixed, hemisectioned when necessary, and first served for the double in situ hybridization, with two sequential chromogenic reactions. They were postfixed, and the labeled cells were retraced immunohistochemically. Finally, the pigment of the embryos was bleached to obtain a clear view. We applied this method to a blastomere transplantation experiment to examine whether the spatial gene expression patterns along the anteroposterior axis can be induced by cell to cell interactions. The presumptive organizer of a 32-cell embryo was replaced by the labeled presumptive epidermis of another synchronous embryo. The resultant triple-stained late gastrula showed quite similar anteroposterior expression patterns of gsc and Xbra to those of a normal embryo in the axial mesoderm derived from the transplanted presumptive epidermis, indicating that cell to cell interactions had induced these patterns. [ABSTRACT FROM AUTHOR]

We developed the RHiNET-2/SW high-speed network switch for a high-throughput parallel computing system consisting of optically interconnected distributed personal computers (PCs). RHiNET-2/SW enables high-throughput network switching (64 Gbit/s) by means of a switching LSI and eight pairs of synchronized parallel optical interconnection modules. To confirm the reliability of RHiNET-2/SW, we measured its bit error rate (BER), which was less than 10-11 (estimated value: 10-20). Five RHiNET-2/SWs and sixteen PC nodes can perform parallel computing. This result demonstrates the feasibility of optical interconnection in a high-speed, flexible network in a parallel computing system. © 2002 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 85(6): 1–10, 2002; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10022 [ABSTRACT FROM AUTHOR]

The authors have developed a communications architecture called RHiNET that is capable of high-performance parallel processing by interconnecting PCs and WSs. RHiNET uses not only computers concentrated in one place but also computers used for daily business within buildings and within floors for parallel processing. Networks used by RHiNET should have high effective bandwidths and small latencies for high-efficiency computing, as well as link lengths for connecting the computers within buildings and floors and a free topology. The former requirements are not satisfied sufficiently by the conventional LANs, while the latter is not satisfied by SANs which are used in cluster systems. RHiNET satisfies both conditions by using a switch having a large memory capacity. In this paper, the architecture and implementation of the RHiNET/SW1 switch used by RHiNET networks are discussed. A scheme called virtual cache is used in RHiNET/SW1 such that a large-capacity packet buffer is installed by SRAM outside the switch ASIC. In addition, the performance of the switch is evaluated by a simulator. © 2001 Scripta Technica, Syst Comp Jpn, 32(14): 24–33, 2001 [ABSTRACT FROM AUTHOR]

LOGIQUE (LOGIc simulation with QUEry) is a parallel logic simulation algorithm for parallel machines with a shared memory. In order to make the best use of the parallelism, queries are issued aggressively. The large overhead in the traditional query-based parallel discrete event simulation (PDES) algorithm is reduced by replacing the query message with a reference to the shared variables. LOGIQUE has been implemented on a multiprocessor and used to simulate logic circuits. The results, which demonstrate the efficiency of LOGIQUE, are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a concurrent description language called NCC for scientific calculations that are executed on a multiprocessor. NCC is based on a static concurrent process model called "NC model." NCC's minimal features allow scientific calculations to be efficiently executed on a large- scale multiprocessor. Having obtained less overhead in execution by restricting NCC's ability to describe concurrent processes, NCC allows users to write scientific calculation programs which are both highly easy to analyze and read. [ABSTRACT FROM AUTHOR]