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Graphene is a promising candidate for future electronic applications. Manufacturing graphene-based electronic devices typically requires graphene transfer from its growth substrate to another desired substrate. This key step for device integration must be applicable at the wafer level and meet the stringent requirements of semiconductor fabrication lines. In this work, wet and semidry transfer (i.e. wafer bonding) are evaluated regarding wafer scalability, handling, potential for automation, yield, contamination, and electrical performance. A wafer scale tool is developed to transfer graphene from 150 mm copper foils to 200 mm silicon wafers without adhesive intermediate polymers. The transferred graphene coverage ranges from 97.9 % to 99.2 % for wet transfer and from 17.2 % to 90.8 % for semidry transfer, with average copper contaminations of 4.7 × 1013 (wet) and 8.2 × 1012 atoms/cm2 (semidry). The corresponding electrical sheet resistance extracted from terahertz timedomain spectroscopy varied from 450 to 550 O sq-1 for wet transfer and from 1000 to 1650 O sq-1 for semidry transfer. Although the wet transfer is superior in terms of yield, carbon contamination level, and electrical quality, wafer bonding yields lower copper contamination levels and provides scalability due to existing industrial tools and processes. Our conclusions can be generalized to all 2D materials. [ABSTRACT FROM AUTHOR]

Tungsten diselenide (WSe 2 ) field-effect transistors (FETs) are promising for emerging electronics because of their tunable polarity, enabling complementary transistor technology, and their suitability for flexible electronics through material transfer. In this work, we demonstrate flexible p-type WSe 2 FETs with absolute drain currents | I D | up to 7 μA/μm. We achieve this by fabricating flexible top-gated FETs with a combined WSe 2 and metal contact transfer approach using WSe 2 grown by metal-organic chemical vapor deposition on sapphire. Despite moderate WSe 2 crystal grain size, our devices show similar or higher | I D | and I D on/off ratio (∼10 5 ) compared to most devices with exfoliated single-crystal WSe 2 from the literature. We analyze charge trapping in our devices using pulsed and bias stress measurements. Notably, the high | I D | values are preserved during pulsing, where charge trapping is minimized. Overall, we demonstrate a fabrication approach advantageous for high drain currents in flexible 2D transistors.

Suspended membranes of monatomic graphene exhibit great potential for applications in electronic and nanoelectromechanical devices. In this work, a "hot and dry" transfer process is demonstrated to address the fabrication and patterning challenges of large-area graphene membranes on top of closed, sealed cavities. Here, "hot" refers to the use of high temperature during transfer, promoting the adhesion. Additionally, "dry" refers to the absence of liquids when graphene and target substrate are brought into contact. The method leads to higher yields of intact suspended monolayer chemical vapor deposition (CVD) graphene and artificially stacked double-layer CVD graphene membranes than previously reported. The yield evaluation is performed using neural-network-based object detection in scanning electron microscopy (SEM) images, ascertaining high yields of intact membranes with large statistical accuracy. The suspended membranes are examined by Raman tomography and atomic force microscopy (AFM). The method is verified by applying the suspended graphene devices as piezoresistive pressure sensors. Our technology advances the application of suspended graphene membranes and can be extended to other two-dimensional materials.