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This paper presents a programme of designing 32 bit high-performance adder with semb dynamic circuit. With modified output carry logic in sparse-tree structure, the semi-dynamic adder circuit, which includes skew-tolerant dynamic domino-circuit and static circuit, and its multiple clocks timing scheme were designed. The different transistor's sizes of adder were designed to fit the different loads and drive conditions of the adder. In SMIC 1.8 V 0. 18 am technology, the simulation results under different conditions show that the designed adder has a high performance. [ABSTRACT FROM AUTHOR]