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The effect of channel width and length shrinking on hot carrier effect (HCE) in standard bulk Si CMOS and SOI CMOS nMOSFETs is studied. The experimental results show that the HCE degradation enhances with the decrease of channel length both in the standard bulk Si and SOI nMOSFETs. However, the channel width shrinking shows different effect on HCE degradation. The HCE degradation enhances with the decrease of channel width in bulk nMOSFETs while the HCE degradation reduces with the decrease of channel length in SOI nMOSFETs. The effect of interface traps on HCE is discussed in order to discover the main physical mechanism. Meanwhile, the effect of border electric field distribution on HCE is discussed so as to explain the underlaid mechanism. The result can be a guide in making a choice of the device size and layout in IC design in practical deep submicron technology. [ABSTRACT FROM AUTHOR]