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An efficient compact encoding process with the pipelining design of Low Density Parity Check (LDPC) Encoder with a two stage, three stage and Maximal Rate Pipelining (MRP) structures are proposed in this work. Comparatively, LDPC encoding is more complex than decoding. The complexity mainly referred to the mathematical computation involved in the design of LDPC encoder. There are several methods used to design reduced parity check matrix, one of the methods involved is the Gauss Elimination method. Conventional and wave pipelining techniques are implemented to overcome the disadvantages of the area, latency, etc., The designed architectures are synthesized in SYNOPSYS tool and implemented in the XC3S-250E FPGA device. The overheads like power and area are efficiently reduced by wave pipelining and their efficiency can be proved by synthesis report. This showcases that the LDPC Encoders require less memory by using MRP structure.

High peak to average power ratio (PAPR) of OFDM reduces the transmitter power efficiency and increases the complication in hardware implementation. A number of techniques have been developed to minimize PAPR of OFDM. Among these techniques, iterative clipping and filtering (ICF) is an effective recent technique that produces significant results in minimizing PAPR. But, the major limitation of this approach is that it requires several iterations for minimizing PAPR. In order to overcome the above limitation, an optimization based ICF is used in this research work. An efficient custom optimized adaptive clipping and filtering technique is proposed. The proposed method shows a greater reduction in PAPR in lesser iterations with reduced out-of-band distortion and bit error rate when compared over classical clipping techniques. Moreover, the effects of oversampling on the performance of the proposed OFDM system are also evaluated.