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Electrochemical methods have been widely used in the chemical and pharmaceutical industries, which require accurate concentration measurements, chemical reaction detections and analyses. The electrochemical potentiostat, the core element in electrochemical instruments, have been discussed as a hot topic addressing the difficulty of applying high-precision constant voltage and picoampere current measurements. Meanwhile, reliable potentiostats are in demand for complicated industrial environments with noises as well as requirements of remotemonitors. This paper describes a potentiostat for industrial glucose measurement that is not only accurate but also fault tolerant to guarantee high reliability in industrial environments. The instrument uses standard industrial communication protocols, profibus, and a 4–20 mA current loop, for remote control and monitoring. Experimental results show that this design has 0.01% accuracy with 1 mV resolution for voltage applications and 0.01% accuracy with 1 pA resolution for current measurements. The design is also shown to be highly reliable in noisy environments.

Register allocation in high-level circuit synthesis is important not only for reducing area, delay, and power overheads, but also for improving the testability of the synthesized circuits. This paper presents an improved register allocation algorithm that improves the testability called weighted graph-based balanced register allocation for high-level circuit synthesis. The controllability and observability of the registers and the self-loop elimination are analyzed to form a weighted conflict graph, where the weight of the edge between two nodes denotes the tendency of the two variables to share the same register. Then the modified desaturation algorithm is used to dynamically modify the weights to obtain a final balanced register allocation which improves the testability of the synthesized circuits. Tests on some benchmarks show that the algorithm gives a higher fault coverage than other algorithms with less area overhead and even less time delay.

Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.

Balanced wrapper scan chains are desirable for system-on-chip (SoC) testing because they minimize the time required to transport the test data. A new heuristic algorithm is proposed based on mean-value approximation and implement fast re-optimization as a subsequence of an earlier best-fit-decrease (BFD) method. The mean length of each scan chain was introduced as an approximation target to balance different scan chains and hence saved testing time. Experimental results present both for assumed arbitrary cores and cores from ITC'02 benchmark and show the effectiveness of the algorithm. The proposed algorithm can provide more balanced wrapper design efficiently for the test scheduling stage.

A test strategy for analog filters was proposed. The output voltage and supply current of the circuit were monitored when using the oscillation test technique. The frequency, average value, maximum value and amplitude of both output voltage and supply current were taken as test parameters. Tolerance bands of test parameters were analyzed. Fault detectabilities of test parameters were compared and combined, and optimal parameter sets were derived. Experimental results show that both the output voltage and supply current give significant contribution to fault detection. Considering catastrophic, single and double parametric faults, the fault coverage in testing the benchmark circuit can be raised from 90.6% for traditional voltage-only oscillation test strategy to 97.2% by monitoring both output voltage and current parameters.

This paper presents a fault-tolerant computer system. It is designed as a double 2-out-of-2 architecture based on component redundant technique. Also, a quantitative probabilistic model is presented for evaluating the reliability, availability, maintainability and safety (RAMS) of this architecture. Hierarchical modeling method and Markov modeling method are used in RAMS analysis to evaluate the system characteristics. The double 2-out-of-2 system is compared with the other two systems, all voting triple modular redundancy (AVTMR) system and dual-duplex system. According to the result, the double 2-out-of-2 system has the highest dependability. Especially, the system can satisfy the safety integrity level (SIL) 4, which means the system's probability of catastrophic failure less than or equal to 10 −8 per hour, therefore, it can be applied to life critical systems such as high-speed railway systems.

Fault diagnosis is very important for development and maintenance of safe and reliable electronic circuits and systems. This paper describes an approach of soft fault diagnosis for analog circuits based on slope fault feature and back propagation neural networks (BPNN). The reported approach uses the voltage relation function between two nodes as fault features; and for linear analog circuits, the voltage relation function is a linear function, thus the slope is invariant as fault feature. Therefore, a unified fault feature for both hard fault (open or short fault) and soft fault (parametric fault) is extracted. Unlike other NN-based diagnosis methods which utilize node voltages or frequency response as fault features, the reported BPNN is trained by the extracted feature vectors, the slope features are calculated by just simulating once for each component, and the trained BPNN can achieve all the soft faults diagnosis of the component. Experiments show that our approach is promising.