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Abstract: Epitaxial Cu(001) layers were deposited on MgO(001) substrates by magnetron sputtering and the atomic structure of the Cu–MgO interface was characterized by spherical aberration (C S )-corrected high-resolution transmission electron microscopy (HRTEM). The interface structure and the misfit dislocation network were determined by imaging in both the <100> and <110> directions. The dislocation network was found to lie along the <100> directions with a Burgers vector of ½ a Cu <100> deduced from HRTEM images and geometrical phase analysis. The dislocations do not fully accommodate the lattice mismatch, yielding residual stress at the interface and an elongation of the Cu lattice along the [001] direction. [ABSTRACT FROM AUTHOR]

Abstract: A high-performance ZnO thin film transistor （ZnO-TFT） with SiO2/Ta2O5/SiO2 (STS) multilayer gate insulator is fabricated by sputtering at room temperature. Compared to ZnO-TFTs with sputtering SiO2 gate insulator, its electrical characteristics are significantly improved, such as the field effect mobility enhanced from 11.2 to 52.4cm2/V s, threshold voltage decreased from 4.2 to 2V, and sub-threshold swing improved from 0.61 to 0.28V/dec. The improvements are attributed to the high gate capacitance (from 50 to 150nF/cm2) as well as nice surface morphology by using dielectric with high～k Ta2O5 sandwiched by SiO2 layers. The capacitance–voltage characteristic of a metal–insulator–semiconductor capacitor with the structure of Indium Tin Oxide/STS/ZnO/Al was investigated and the trap charges at the interface or bulk is evaluated to be 2.24×1012 cm− 2. From the slope of C− 2 versus gate voltage, the doping density ND of ZnO is estimated to be 1.49×1016 cm− 3. [Copyright &y& Elsevier]

Abstract: Top-contact Copper phthalocyanine (CuPc) thin-film field-effect transistor (TFT) with SiO2/Ta2O5/SiO2 (STS) multilayer as the dielectric was fabricated and investigated. With the multi-layer dielectric, drive voltage was remarkably reduced. A relatively large on-current of 1.1×10− 7 A at a VGS of −15V was obtained due to the strong coupling capability provided by the STS multilayer gate insulator. The device shows a moderate performance: saturation mobility of μ sat =6.12×10− 4 cm2/Vs, on-current to off-current ratio of I on/I off =1.1×103, threshold voltage of V TH =−3.2V and sub-threshold swing SS=1.6V/dec. Atomic force microscope images show that the STS multilayer has a relative smooth surface. Experiment results indicate that STS multilayer is a promising insulator for the low drive voltage CuPc-based TFTs. [Copyright &y& Elsevier]