Search

Graphene is a 2D material with extraordinary electronic and mechanical properties and has a wide range of applications. Among existing synthesis methods, chemical vapor deposition (CVD) onto Cu foil is the most prominent because it allows large area high quality graphene to be prepared at relatively low costs and then subsequently wet transferred to arbitrary substrates. Typically, PMMA and FeCl 3 are used as a polymeric support layer and a metal etchant respectively during wet transfer. Unfortunately, this method leaves graphene susceptible to contamination, degrading transferred graphene's extraordinary properties. In this paper, contamination in the form of black particulates is identified to be Fe wrapped in graphene and a model of how it originates was developed. Then, a procedure to reduce this contamination during wet transfer was developed and its effectiveness was systematically studied. Transfers were characterized using Raman spectroscopy and optical microscopy with image segmentation. Experimental data obtained indicates that this simple and economic method is very effective in reducing Fe contamination on transferred CVD graphene, offering a way to improve the wet transfer process.

The method of controlling dislocation positions via local oxidation of 80 nm thick Si 0.8 Ge 0.2 buffer layer on Si substrate is investigated. The strained SiGe layer is locally exposed to oxidation by patterning Si 3 N 4 mask layer on SiGe with perpendicularly crossing stripe patterns with directions. The local oxidation of patterned SiGe regions leads to increased stress to the remaining SiGe either via Ge pileup or volume expansion during oxidation. The increased stress in the SiGe region underneath the oxide increases dislocation nucleation rate. The preferential nucleation of dislocations and subsequent propagation of dislocations through non-oxidized regions results in reduced threading dislocation density to 10 6 – 7 /cm 2 , which is lower than that of the conventional constant composition SiGe buffer layer. Further reduction of threading dislocation density is expected by optimizing the oxidation conditions and pattern size and shape for local oxidation.

We present the results of a systematic study of chemical vapor deposition of graphene on silicon substrates. The silicon substrate is covered with SiO 2 and capped with an electron-beam evaporator deposited nickel film, which serves as the catalyst for carbon precursor decomposition. Methane is used as the carbon precursor. Three key parameters of CVD growths, the growth temperature, time, and the post-growth cooling rate are studied and the optimized combination of the three allowed for the reproducible fabrication of single layer graphene of larger than 100 μm 2 covering more than 50% of the surface of 1-in. diameter Si wafers. We further demonstrate the transfer of CVD graphene onto SiO 2 /Si surfaces with higher than 95% success rate. Our result together with those reported by other research groups shows real promise of the integration of carbon electronics with silicon integrated circuit technology.

We present a review of the progress in the field of 2DEG in strained Si/SiGe heterostructures during the past 20 or so years. We highlight the difference in the key challenges in sample preparation between the samples for low-temperature transport studies and those for field-effect transistor (FET) applications. The requirements of low electron density and high electron mobility for low-temperature electron transport are also discussed. High mobility (> 300,000 cm2/V s) can be reproducibly achieved recently and low electron sheet density (1.1 × 1011 cm− 2) in modulation-doped samples (as opposed to gated) has also been observed. Magnetotransport measurements provide indications of the mobility limiting factors thereby pointing to the plausible directions for further improvements on the strained Si sample quality.

This paper presents a method for fabricating uniaxially as well as biaxially strained Si films on porous Si substrates. Single crystalline Si films of ~ 150 nm thickness on top of porous Si substrate can be routinely obtained by self-limiting anodization of heavily doped p-type substrates with epitaxially grown thin Si overlayers. The typical structure of our samples has the porous Si region in square shape in the center of the sample surrounded by bulk Si analogous to a picture in a frame. The porous Si region undergoes volume expansion upon oxidation at low temperature (~ 500 °C) in steam. The rigid bulk Si frame constrains the porous Si region preventing it from expansion along the direction of the substrate surface. The expansion can be either uniaxial or biaxial along the sample surface if two opposite stripes of bulk Si or all four sides are removed. In this report, we describe uniaxial tensile strain of 0.83% observed in a 150 nm thick Si film without dislocation or crack.

The topic of guided self-assembly of Ge and InAs quantum dots on Si (001) substrates via epitaxy is discussed. A buried misfit dislocation network can be used to guide the assembly process through the associated strain field. Patterned substrates can also be used to guide the assembly process. This paper discusses the recent experimental and theoretical studies of the guided assembly process with an emphasis on what remains to be understood.

InAs self-assembled quantum dots (QDs) were grown on Si (001) substrates via molecular beam epitaxy. The size distribution and density of InAs QDs grown under different conditions were studied using plan-view transmission electron microscopy. Dot density was shown to strongly depend on arsenic beam equivalent pressure (BEP) ranging from 2.8×10 -5 to 1.2×10 -3 Pa. In contrast, dot density was nearly independent of substrate temperature from 295 to 410 °C under constant arsenic BEP, while broadening of size distribution was observed with increasing temperature. The mechanism accounting for some of the main features of the experimental observations is discussed. Finally, InAs quantum dots with optimized narrow size distribution and high density were grown at low arsenic BEP of 7.2 ×10 -5 Pa and low temperature of 250 °C followed by annealing at arsenic BEP of 1.9 ×10 -4 Pa and temperature of 410 °C.

L'approche concernant l'utilisation de support a gradin dans le but de la prevention contre la formation de dislocations n'est pas valable dans le cas de structures heteroepitaxiques obtenues par de techniques epitaxiques de croissance