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Since the introduction of 248 and 193 nm lithography sub-pellicle contamination has been a significant problem and a major contributor to reticle costs and semiconductor yield losses. The most common contaminant identified has been ammonium sulfate commonly called haze, however there have been many other contaminants identified and grouped in the category as haze. In attempts to mitigate the cause of this problem various processes and manufacturing protocols have been put in place to either prevent the problem or identify the source of the problem before there is a negative impact in the wafer fab. In spite of efforts to manage the effects of sub-pellicle contamination in the wafer fab, the problem continues to exist. Over the years we have identified many of the compounds and their sources that exist on the sub-pellicle surface, however one has been elusive. This paper will provide both the identification of this compound and its source.

We have developed a new focus measurement method based on analyzing SEM images that can help to control a scanner. In advanced semiconductor fabrication, rigorous focus control of the scanner has been required because focus error causes a defect. Therefore, it is essential to ensure focus error are detected at wafer fabrication. In the past, the focus has been measured using test patterns made outside of the chip by optical metrology system. Thus, present focus metrology system can’t measure the focus of an arbitrary point in the chip. The new method enables a highly precise focus measurement of the arbitrary point of the chip based on a focus plane of a reference scanner. The method estimates the focus amount by analyzing side wall shapes of circuit patterns of SEM images. Side wall shapes are quantified using multisliced contours extracted from SEM-images high accuracy. By using this method, it is possible to measure the focus of the arbitrary circuit pattern area of the chip without a test pattern. We believe the method can contribute to control the scanner and to detect hot spots which appear by focus error. This new method and the evaluation results will be presented in detail in this paper.

Advancing technology nodes with smaller process margins require improved photolithography overlay control. Overlay control at develop inspection (DI) based on optical metrology targets is well established in semiconductor manufacturing. Advances in target design and metrology technology have enabled significant improvements in overlay precision and accuracy. One approach to represent in-die on-device as-etched overlay is to measure at final inspection (FI) with a scanning electron microscope (SEM). Disadvantages to this approach include inability to rework, limited layer coverage due to lack of transparency, and higher cost of ownership (CoO). A hybrid approach is investigated in this report whereby infrequent DI/FI bias is characterized and the results are used to compensate the frequent DI overlay results. The bias characterization is done on an infrequent basis, either based on time or triggered from change points. On a per-device and per-layer basis, the optical target overlay at DI is compared with SEM on-device overlay at FI. The bias characterization results are validated and tracked for use in compensating the DI APC controller. Results of the DI/FI bias characterization and sources of variation are presented, as well as the impact on the DI correctables feeding the APC system. Implementation details in a high volume manufacturing (HVM) wafer fab will be reviewed. Finally future directions of the investigation will be discussed.

Aerial image measurement is a key technique for model based optical proximity correction (OPC) verification. Actual aerial images obtained by AIMS (aerial image measurement system) or WLCD (wafer level critical dimension) can detect printed wafer weak point structures in advance of wafer exposure and defect inspection. Normally, the potential wafer weak points are determined based on optical rule check (ORC) simulation in advance. However, the correlation to real wafer weak points is often not perfect due to the contribution of mask three dimension (M3D) effects, actual mask errors, and scanner lens effects. If the design weak points can accurately be detected in advance, it will reduce the wafer fab cost and improve cycle time. WLCD or AIMS tools are able to measure the aerial images CD and bossung curve through focus window. However, it is difficult to detect the wafer weak point in advance without defining selection criteria. In this study, wafer weak points sensitive to mask mean-to-nominal values are characterized for a process with very high MEEF (normally more than 4). Aerial image CD uses fixed threshold to detect the wafer weak points. By using WLCD through threshold and focus window, the efficiency of wafer weak point detection is also demonstrated. A novel method using contrast range evaluation is shown in the paper. Use of the slope of aerial images for more accurate detection of the wafer weak points using WLCD is also discussed. The contrast range can also be used to detect the wafer weak points in advance. Further, since the mean to nominal of the reticle contributes to the effective contrast range in a high MEEF area this work shows that control of the mask error is critical for high MEEF layers such as poly, active and metal layers. Wafer process based weak points that cannot be detected by wafer lithography CD or WLCD will be discussed.

The new device architectures and materials being introduced for sub-10nm manufacturing, combined with the complexity of multiple patterning and the need for improved hotspot detection strategies, have pushed current wafer inspection technologies to their limits. In parallel, gaps in mask inspection capability are growing as new generations of mask technologies are developed to support these sub-10nm wafer manufacturing requirements. In particular, the challenges associated with nanoimprint and extreme ultraviolet (EUV) mask inspection require new strategies that enable fast inspection at high sensitivity. The tradeoffs between sensitivity and throughput for optical and e-beam inspection are well understood. Optical inspection offers the highest throughput and is the current workhorse of the industry for both wafer and mask inspection. E-beam inspection offers the highest sensitivity but has historically lacked the throughput required for widespread adoption in the manufacturing environment. It is unlikely that continued incremental improvements to either technology will meet tomorrow’s requirements, and therefore a new inspection technology approach is required; one that combines the high-throughput performance of optical with the high-sensitivity capabilities of e-beam inspection. To support the industry in meeting these challenges SUNY Poly SEMATECH has evaluated disruptive technologies that can meet the requirements for high volume manufacturing (HVM), for both the wafer fab [1] and the mask shop. Highspeed massively parallel e-beam defect inspection has been identified as the leading candidate for addressing the key gaps limiting today’s patterned defect inspection techniques. As of late 2014 SUNY Poly SEMATECH completed a review, system analysis, and proof of concept evaluation of multiple e-beam technologies for defect inspection. A champion approach has been identified based on a multibeam technology from Carl Zeiss. This paper includes a discussion on the need for high-speed e-beam inspection and then provides initial imaging results from EUV masks and wafers from 61 and 91 beam demonstration systems. Progress towards high resolution and consistent intentional defect arrays (IDA) is also shown.

The partnership between RVS, Seek Thermal and Freescale Semiconductor continues on the path to bring the latest technology and innovation to both military and commercial customers. The partnership has matured the 17μm pixel for volume production on the Thermal Weapon Sight (TWS) program in efforts to bring advanced production capability to produce a low cost, high performance product. The partnership has developed the 12μm pixel and has demonstrated performance across a family of detector sizes ranging from formats as small as 206 x 156 to full high definition formats. Detector pixel sensitivities have been achieved using the RVS double level advanced pixel structure. Transition of the packaging of microbolometers from a traditional die level package to a wafer level package (WLP) in a high volume commercial environment is complete. Innovations in wafer fabrication techniques have been incorporated into this product line to assist in the high yield required for volume production. The WLP seal yield is currently > 95%. Simulated package vacuum lives >> 20 years have been demonstrated through accelerated life testing where the package has been shown to have no degradation after 2,500 hours at 150°C. Additionally the rugged assembly has shown no degradation after mechanical shock and vibration and thermal shock testing. The transition to production effort was successfully completed in 2014 and the WLP design has been integrated into multiple new production products including the TWS and the innovative Seek Thermal commercial product that interfaces directly to an iPhone or android device.

Historical data indicates reticle write times are increasing node-to-node. The cost of mask sets is increasing driven by the tighter requirements and more levels. The regular introduction of new generations of mask patterning tools with improved performance is unable to fully compensate for the increased data and complexity required. Write time is a primary metric that drives mask fabrication speed. Design (Raw data) is only the first step in the process and many interactions between mask and wafer technology such as OPC used, OPC efficiency for writers, fracture engines, and actual field size used drive total write time. Yield, technology, and inspection rules drive the remaining raw cycle time. Yield can be even more critical for speed of delivery as it drives re-writes and wasted time. While intrinsic process yield is important, repair capability is the reason mask delivery is still able to deliver 100% good reticles to the fab. Advanced nodes utilizing several layers of multiple patterning may require mask writer tool dedication to meet image placement specifications. This will increase the effective mask cycle time for a layer mask set and drive the need for additional mask write capability in order to deliver masks at the rate required by the wafer fab production schedules.

A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity and variability. The work described here is motivated by requirements for extreme accuracy and control of variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design of VSB shots and dose assignment.

The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been promoted in the semiconductor industry which has been shown to suppress or minimize the propensity for haze formation, but none of these technologies can stop every instance of haze. Fortunately, a novel technology which uses a dry (no chemical effluents) removal system, laser-based, through pellicle process has been reported recently. The technology presented here avoids many of the shortcomings of the wet clean process mentioned previously. The dry clean process extends the life of the photomask; maintains more consistent CD’s, phase, and transmission; avoids adjustment to the exposure dose to account for photomask changes, reduces the number of required inspections and otherwise improves the efficiency and predictability of the lithography cell. We report on the performance of photomask based on a design developed to study the impact of metrology variations on dry clean process. In a first step we focus on basic characteristics: CD variation, phase, Cr/MoSi transmission, pellicle transmission, registration variations. In a second step, we evaluate haze removal and prevention performance and wafer photo margin. Haze removal is studied on the masks for several haze types and various exposure conditions. The results of this study show that some of metrology variation are likely to be a problem at high technology node, and haze removal performance is determined whether the component of haze is remained or not after treatment.

According to the road map shown in ITRS [1], the EUV mask requirement for defect inspection is to detect the defect size of sub- 20 nm in the near future. EB (Electron Beam) inspection with high resolution is one of the promising candidates to meet such severe defect inspection requirements. However, conventional EB inspection using the SEM method has the problem of low throughput. Therefore, we have developed an EB inspection tool, named Model EBEYE M※. The tool has the PEM (Projection Electron Microscope) technique and the image acquisition technique with TDI (Time Delay Integration) sensor while moving the stage continuously to achieve high throughput [2]. In our previous study, we showed the performance of the tool applied for the half pitch (hp) 2X nm node in a production phase for particle inspection on an EUV blank. In the study, the sensitivity of 20 nm with capture rate of 100 % and the throughput of 1 hour per 100 mm square were achieved, which was higher than the conventional optical inspection tool for EUV mask inspection [3]-[5]. Such particle inspection is called for not only on the EUV blank but also on the patterned EUV mask. It is required after defect repair and final cleaning for EUV mask fabrication. Moreover, it is useful as a particle monitoring tool between a certain numbers of exposures for wafer fabrication because EUV pellicle has not been ready yet. However, since the patterned EUV mask consists of 3D structure, it is more difficult than that on the EUV blank. In this paper, we evaluated that the particle inspection on the EUV blank using the tool which was applied for the patterned EUV mask. Moreover, the capability of the particle inspection on the patterned EUV mask for the hp 2X nm node, whose target is 25 nm of the sensitivity, was confirmed. As a result, the inspection and SEM review results of the patterned EUV masks revealed that the sensitivity of the hp 100 nm Line/Space (LS) was 25 nm and that of the hp 140- 160 nm Contact Hole (CH) was 21 nm. Therefore, we confirmed that particle inspection on the patterned EUV mask using Model EBEYE M could be available for the EUV mask of the hp 2X nm node. In the future, we will try to inspect the production mask of the hp 2X nm node, and try to confirm the performance for the EUV mask of the hp 1X nm node.

Requalifying semiconductor photomasks remains critically important and is increasingly challenging for 20nm and 14nm node logic reticles. Patterns are becoming more complex on the photomask, and defect sensitivity requirements are more stringent than ever before. Reticle inspection tools are equally important for effective process development and the successful ramp and sustained yield for high volume manufacturing. The inspection stages considered were: incoming inspection to match with Mask Shop Outgoing result and to detect defects generated during transport; requalification by routine cycle inspection to detect Haze and any other defects; and inspection by in-house or Mask shop at the post cleaning. There are many critical capability and capacity factors for the decision for best inspection tool and strategy for high volume manufacturing, especially objective Lens NA, wavelength, power, pixel size, throughput, full-automation inspection linked with Overhead Transport, algorithm application, engineering application function, and inspection of PSM and OMOG . These tools are expensive but deliver differentiated value in terms of performance and throughput as well as extendibility. Performing a thorough evaluation and making a technically sound choice which explores these many factors is critical for success of a fab. This paper examines the methodology for evaluating two different photomask inspection tools. The focus is on ensuring production worthiness on real and advanced product photomasks requiring accurate evaluation of sensitivity, throughput, data analysis function and engineering work function on those product photomasks. Photomasks used for data collection are production reticles, PDM(Program defect Mask), SiN spray defect Reticle which is described that evaluates how the tools would perform on a contaminated plate.

The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles “hopping” between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present “black-border” solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.

Avago’s 850nm VCSELs for applications requiring modulation at 25-28Gbps have been designed for -3dB bandwidths in excess of 19GHz over the extended temperature range of 0-85°C. The DBR mirrors have been optimized to minimize optical losses and thermal and electrical resistance. The active region is designed to provide superior differential gain for high optical bandwidth. In this paper we will describe the design for performance and manufacturability of Avago’s high speed 25-28Gbps VCSEL. Analysis of the high-speed modulation characteristics and results of wearout reliability studies will be presented. We will also discuss the manufacturability of this next generation of high performance, reliable lasers. The challenges of epitaxial growth and wafer fabrication along with the associated process control technologies will be described.

As dimension of device shrinks to 1X nm node, an extreme control of critical dimension uniformity (CDU) of masks becomes one of key techniques for mask and wafer fabrication. For memory devices, a large number of optical techniques have been studied and applied to mask production so far. The advantages of these methods are to eliminate the sampling dependency due to their high throughput, to minimize the local CD errors due to their large field of view (FOV) and to improve the correlation with wafer infield uniformity if they have scanner-like optics. For logic devices, however, CD-SEM has been a single solution to characterize CD performance of logic masks for a long time and simple monitoring patterns, instead of the cell patterns, have been measured to monitor the CD quality of masks. Therefore a global CDU of the mask tends to show its ambiguity because of the limited number of measurement sites and large local CD errors. An application of optical metrology for logic mask is a challenging task because patterns are more complex and random in shape and because there is no guarantee of finding patterns for CDU everywhere on the mask. CDU map still consists of the results from the indirect measurements and the traditional definition of uniformity, a statistical deviation of a typical pattern, seems to be unsuitable for logic CDU. A new definition of CDU is required in order to maximize the coverage area on a mask. In this study, we have focused of the possibility of measuring cell patterns and of using an inspection tool with data base handling capability, KLA Teron617, to find the areas and positions where the repeating patterns exist and the patterns which satisfy a certain set of condition and we have devised a new definition of CDU, which can handle multiple target CDs. Then we have checked the feasibility and validity of our new methodology through evaluation its fundamental performance such as accuracy, repeatability, and correlation with other CD metrology tools with a set of logic masks.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continue to diminish, and so do mask defect requirements due to increasing MEEF. Post-inspection, mask defects have traditionally been classified by operators manually based on visual review. This approach may have worked down to 65/55nm node layers. However, starting 45nm and smaller nodes, visually reviewing 50 to sometimes 100s of defects on masks with complex modelbased OPC, SRAF, and ILT geometries, is error-prone and takes up valuable inspection tool capacity. Both these shortcomings in manual defect review are overcome by adoption of the computational solution called Automated Defect Classification (ADC) wherein mask defects are accurately classified within seconds and consistent to guidelines used by production technicians and engineers.

One of the objectives of a robust optical proximity correction (OPC) model is to simulate the process variation including 3D mask effects or mask models for different mask blanks. Assuming that the data of different reticle blanks is the same, the wafer data should be a close match for the same OPC model. In order to enhance the robustness of the OPC model, the 3D mask effects need to be reduced. A test of this would be to ensure a close match of the so called fingerprints of different reticle blanks at the wafer level. Features for fingerprint test patterns include “critical dimension through pitch” (CDTP), “inverse CDTP”, and “linearity patterns” and critical dimension (CD) difference of disposition structures. In this manuscript the proximity matching of implant layers on chrome on glass (COG) and advance binary reticle blanks will be demonstrated. We will also investigate the influence of reticle blank material including reticle process on isolated and dense features upon the proximity matching for 28 nm high volumes ArF layers such as implant and 2X metal layers. The OPC model verification has been done successfully for both bare wafer and full field wafer for implant layers. There is comparable OPC model for advanced binary and COG reticle. Moreover, the wafer critical dimension uniformity (CDU) results show that advance binary has much better wafer CDU then COG. In spite of higher reticle cost when switching over to advanced binary, there is a considerable cost reduction for the wafer fab which includes a 39% savings in total reticle cost as well as cost reduction due to minimal line holds (LH), wafer reworks and scraps due to Chrome degradation.

Traditionally, product development for reticle defect inspection mostly addressed operational requirements of the mask shops with highly individualized manufacturing. As a result, limited automation capability was available as compared to the standards in wafer production. Wafer fabs are guided by completely different conditions. Thousands of active reticles exist in a single fab requiring frequent re-inspections without interruption of wafer exposures. This requires high throughput of inspection tools, smart management of tool fleet, sophisticated scheduling and in-time execution of reticle inspections linked to the wafer manufacturing. The paper reports about the successful implementation of fully automated reticle defect inspection in a high-volume advanced logic fab. Automation scenarios - created based on existing SEMI standards - included inspection scheduling, reticle transport and inspection tool operation. A considerable productivity gain for the operation of Lasertec MATRICS X700 series inspection tools was obtained. Based on the learning throughout implementation, the requirements to the automation capability and tool operation as well as adjustments to working procedures are discussed.

As a result of repeated cleanings and exposure effects such as chrome migration or MoSi oxidation some photomasks in the semiconductor fabs exhibit changes in critical dimension uniformity (CDU) over time. Detecting these effects in a timely manner allows for better risk management and process control in manufacturing. By monitoring changes in film reflectance intensity due to the various degradation mechanisms it is possible to predict when they may begin to influence across chip line width variations (ACLV). By accurately predicting the magnitude of these changes it is possible for semiconductor manufacturers to replace the photomasks before they have an impact on yields. This paper looks at possible causes of CDU variations on reticles during use and how this information might be used to improve or monitor reticle CDU changes over time.

As optical lithography continues to extend into low-k1 regime, resolution of mask patterns continues to diminish. The limitation of 1.35 NA posed by water-based lithography has led to the application of various resolution enhancement techniques (RET), for example, use of strong phase-shifting masks, aggressive OPC and sub-resolution assist features, customized illuminators, etc. The adoption of these RET techniques combined with the requirements to detect even smaller defects on masks due to increasing MEEF, poses considerable challenges for a mask inspection engineer. Inspecting masks under their actinic-aerial image conditions would detect defects that are more likely to print under those exposure conditions. However, this also makes reviewing such defects in their low-contrast aerial images very challenging. On the other hand, inspecting masks under higher resolution or mask-plane inspection optics would allow for better viewing of defects post-inspection. However, such inspections generally would also detect many more defects, including critical and nuisance, thereby making it difficult to judge which are of real concern for printability on wafer. Hence, a comprehensive approach is needed in handling defects both post-aerial and post-high resolution inspections. This paper focuses on review of defects post high resolution or mask-plane inspections, especially in the wafer-fab environment. A later paper will focus on review of defects post aerial-image inspections.

The haze nucleation and growth phenomenon on critical photomask surfaces has periodically gained attention as it has significantly impacted wafer printability for different technology nodes over the years. A number of process solutions have been shown to suppress or minimize the propensity for haze formation, but none of these technologies has stopped every instance of haze. Additionally, the management of photo-induced defects during lithography exposure is expensive, so some capability will always be needed to remove haze on photomasks for long term maintenance over a mask's lifetime. A novel technology is reviewed here which uses a dry (no chemical effluents) removal system to safely sweep the entire printable region of a pelliclized photomask to eliminate all removable haze. This process is safe regardless of the mask substrate materials or the presence of small critical patterns such as SRAF's that may represent damage problems for traditional cleaning methods. Operational process techniques for this system and performance in removal will be shown for haze located on the mask pattern surface. This paper will also discuss the theory of operation for the system, including expected chemical reactions and address the reformation rate of haze crystals. Data from tool acceptance and preliminary production use will also be reviewed including analysis of process window through a focus-exposure matrix, repair durability, CD performance, and sort yield.

Historically, photomask and wafer cleaning have been considered trivial tasks. The primary challenge had been simply the removal of particles that may have an impact on final product yield. As wavelengths decrease and energy on the image plane of the reticle increase, the degree and complexity of surface contaminants on the reticle become a more complicated challenge. The result is that the mask fabricator is faced with two new challenges; reducing and identifying the types of contaminants on the reticle prior to exposure in the wafer fab and eliminating contaminants that have been deposited in the fab. These contaminants are often different in that 193nm exposure produces higher molecular weight contaminants that can be more difficult to remove. While the effects of these contaminants may not be serious for transmissive lithography, their effects can be catastrophic for reflective lithography, such as Extreme Ultra- Violet (EUV) lithography. We will provide results showing the types of contaminants commonly found on various types of reticles and the respective challenges associated with their removal. Additionally, prior to developing an effective cleaning protocol understanding the chemical composition of the substrate is extremely important. We will provide analytical data that will clearly describe the composition of the mask substrates.

EUV lithography (EUVL) is considered the most attractive solution for semiconductor device manufacturing beyond the 22nm half-pitch node. In EUVL, one of the greatest challenges is the lack of a pellicle, which makes EUV masks prone to particle contamination. Therefore, mask cleaning plays an important role in keeping masks clean during both fabrication in the mask shop and usage in the wafer fab. According to the International Technology Roadmap for Semiconductors (ITRS), in 2013 mask cleaning processes should remove all defects larger than 25nm without damaging 78nm and smaller patterns for the 23nm Flash half-pitch node [1]. In addition to contamination concerns, EUV masks introduce new materials and a multilayer structure that is different from the Cr on glass used in traditional optical masks. Physical forces applied by megasonic cleaning to remove particles on an optical mask could damage EUV mask patterns. Thus, it is important to determine the magnitude of the physical forces that can break absorber patterns (TaN or TaBN) from the surface of a Ru-capped MoSi multilayer film. The adhesion of particles of interest to the Ru-capped multilayer should also be measured. In the complex structure of an EUV mask, adhesion forces of particles on the top surface are modified by the different layers beneath the Ru. Hence, it is crucial to directly measure the force required to remove particles and break absorber patterns on EUV mask surfaces to determine the process window for applicable cleaning forces. We used scanning probe microscopy (SPM) to quantify these forces. The SPM probe was precisely controlled to remove particles and break patterns on Ru-capped EUV mask blanks. While being manipulated, the deflection signals of the probe were monitored and then converted to forces using a simple beam model. In this paper, we present the measured breakage forces for absorber patterns as a function of their size and compare them with removal forces for 50nm and 100nm SiO2 and polystyrenelatex (PSL) particles. Based on these data and our analysis, we will demonstrate a process window for physical force that can successfully clean EUV masks beyond the 16nm half-pitch node.

Reticles are contaminated during its lifetime and can catch particles as large as several tens of microns. Such defects on the backside of photomasks are usually considered as uncritical and thus do not receive much attention. Backside defects are out of focus by the mask thickness during wafer exposure and cannot be directly imaged on wafer. However, the shadow of the defects changes the local illumination of the mask patterns and may result in spatial variation of critical dimension (CD) on wafer depending on numerical aperture (NA) and pupil shape. There have been only a few investigations on printability of backside defects in the past, and no data are available for the most advanced technology nodes. Reticles are regularly inspected for particles on the glass side in the wafer fab but limits for acceptable defect size are based on estimations. Detection of non-acceptable particles causes exposed wafers being either delayed or reworked with impact on throughput and cost performance. It is therefore important to gain better understanding of critical sizes of backside defects and of appropriate detection capabilities. We have designed and manufactured a test mask with repeating patterns of 20nm, 28nm and 40nm technology node ranging from contact and line/space critical layers to non-critical implant layers. Programmed chrome defects of varying size are placed on the backside of the mask opposite to the repeating front side patterns in order to measure the spatial variation of transmission and wafer CD caused by the backside defects. The test mask was printed on a bare Silicon wafer and the size of printed features was measured by spatial sampling. Wafer CD variation for different backside defect sizes are demonstrated and compared for 28nm node first metal layer. Although the opaque chrome defects on the backside do not behave like real particles they aim on deriving a print threshold for backside particles based on actual wafer data. After such critical size of backside defects is obtained the reticle was also utilized to investigate the detection ability of backside defects by defect inspection of the reticle.

At the 2010 meeting of the Defense and Security Symposia Raytheon reported on the status of their efforts to establish a high rate uncooled detector manufacturing capability. At that time we had just finished the transition of the 640 × 480, 25 μm product to our 200 mm wafer fab line at Freescale semiconductor and established an automated packaging and test capability. Over the past year we have continued to build on that foundation. In this paper we will report on this year's progress in completing the transition of our 25 μm product line to Freescale semiconductor. Included will be the 320 × 240 product transition and a summary of SPC and defectivity data from one year's production. Looking beyond 25 μm, we are well along in our transition of the 17 μm product line to Freescale, with test results being available for the 640 × 480. Additionally, we will report on progress / status of the Tailwind program, which is developing a 2048 × 1536, 17 μm uncooled sensor. Data to be reported includes the establishment of subfield stitching at a high rate commercial fab and the development of the detector package and electronics. With 17 μm transitioned to production, Raytheon has started work on the HD LWIR program, which is laying the foundation for the next generation of uncooled detectors by further shrinking the pixel to

Improved overlay performance is one of the critical elements in enabling the continuing advancement of the semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay and point out the importance of high density sampling as well as the potential for improved mask qualification and disposition.

Information is 'key'. Timely information in a fab environment provides substantial insight into the Mask quality, process health, steps needed to improve yield and throughout time. Ideal for mask and wafer fabs, the RS-Mini central server brings the inspection tool's terminal to the end user via a desktop application. Hundreds of users can simultaneously classify (with automation capability), annotate repair history, query and summarize year's worth of inspection results with images from tens of tools, as well as establish defect and process health trends in a matter of seconds. The RS-Mini, a low cost, state of the art mask defect management framework delivering a highly integrated rich user experience, fits in a compact rack mountable server blade less than 2 inches in thickness.

In today's semiconductor industry, prior to wafer fabrication, it has become a desirable practice to scan layout designs for lithography-induced defects using advanced process window simulations in conjunction with corresponding manufacturing checks. This methodology has been proven to provide the highest level of accuracy when correlating systematic defects found on the wafer with those identified through simulation. To date, when directly applying this methodology at the full chip level, there has been unfavorable expenses incurred that are associated with simulation which are currently overshadowing its primary benefit of accuracy - namely, long runtimes and the requirement for an abundance of cpus. Considering the aforementioned, the industry has begun to lean towards a more practical application for hotspot identification that revolves around topological pattern recognition in an attempt to sidestep the simulation runtime. This solution can be much less costly when weighing against the negative runtime overhead of simulation. The apparent benefits of pattern matching are, however, counterbalanced with a fundamental concern regarding detection accuracy; topological pattern identification can only detect polygonal configurations, or some derivative of a configuration, which have been previously identified. It is evident that both systems have their strengths and their weaknesses, and that one system's strength is the other's weakness, and vice-versa. A novel hotspot detection methodology that utilizes pattern matching combined with lithographic simulation will be introduced. This system will attempt to minimize the negative aspects of both pattern matching and simulation. The proposed methodology has a high potential to decrease the amount of processing time spent during simulation, to relax the high cpu count requirement, and to maximize pattern matching accuracy by incorporating a multi-staged pattern matching flow prior to performing simulation on a reduced data set. Also brought forth will be an original methodology for constructing the core pattern set, or candidate hotspot library, in conjunction with establishing hotspot and coldspot pattern libraries. Lastly, it will be conveyed how this system can automatically improve its potential as more designs are passed through it.

The Critical Dimension Uniformity (CDU) specification on photo-mask is getting increasingly tighter which each successive node. The ITRS roadmap for optical masks indicates that, the CDU (3 sigma) for dense lines for binary or attenuated phase shift mask is 3.4nm for 45nm half-pitch (45HP) node and will go down to 2.4nm for 32HP node. The current variability in mask shop processes results in CDU variation across the photo-mask of ~2-3nm. Hence, we are entering in a phase where the mask CDU specification is approaching the limit of the capability of the current POR (process on record). Hence, mask shops have started exploring more active mechanisms to improve or compensate for the CDU of the masks. A typical application is in feeding back the CDU data to adjust the mask writer dose and compensate for non-uniformity in the CDs, resulting in improved quality of subsequent masks. Another option is to feed the CD uniformity information forward into the wafer FAB and adjust the scanner dose to correct for reticle non-uniformity. For these purposes mask makers prefer a dense measurement of CDs across the reticle in a short time. Mask makers are currently using the CD-SEM tool for data collection. While the resolution of SEM data ensures its position as the industry standard, an output map of CDU from a reticle inspection tool has the advantage of denser sampling over larger areas on the mask. High NA reticle inspection systems scan the entire reticle at high throughput, and are ideally suited for collecting CDU data on a dense grid. In this paper, we describe the basic theory of a new, reticle inspection-based CDU tool, and results on advanced memory masks. We discuss possible applications of CDU maps for optimizing the mask manufacturing and wafer production processes.

With the projected rollout of pre-production extreme ultraviolet lithography (EUVL) scanners in 2010, EUVL pilot line production will become a reality in wafer fabrication companies. Among EUVL infrastructure items that must be ready, EUV mask carriers remain critical. To keep non-pellicle EUV masks free from particle contamination, an EUV pod concept has been extensively studied. Early prototypes demonstrated nearly particle-free results at a 53 nm PSL equivalent inspection sensitivity during EUVL mask robotic handling, shipment, vacuum pump-purge, and storage. After the passage of SEMI E152, which specifies the EUV pod mechanical interfaces, standards-compliant EUV pod prototypes, including a production version inner pod and prototype outer pod, were built and tested. Their particle protection capability results are reported in this paper. A state-of-the-art blank defect inspection tool was used to quantify their defect protection capability during mask robotic handling, shipment, and storage tests. To ensure the availability of an EUV pod for 2010 pilot production, the progress and preliminary test results of pre-production EUV outer pods are reported as well.

Extensive VCSEL reliability enhancements have been carried out at Emcore in the past year with significant results. In this talk, we will present the failure mechanisms, the method and effectiveness of wafer and die screening, and the approaches to eliminate these failure mechanisms. Results of improved reliability will also be discussed. design optimization, wafer fab process control and automation, and VCSEL chip testing and screening enhancements. As a result of these efforts, Emcore VCSEL's mean time to failure (MMTF) and time to 1% failure rate have improved significantly. In this paper, we summarize recent reliability improvements carried out at Emcore and present the results of these improvement initiatives. We will discuss the effectiveness of wafer and die screening procedures as well as design optimization for the next generation product, aimed at better performance and improved manufacturability. We will present preliminary reliability data from these new devices. In an effort to further assure VCSEL's reliability and minimize down-stream module manufacturing costs, we will also present the work we've been doing on wafer level burn-in.

Presently, most defective problems in silicon based devices can be traced ultimately to stresses developed during various fabrications process stages. If the process induced stresses exceed the critical stress magnitude, dislocations occur to relax the stain. Subsequently, other defects such as cracks, chips and void related to stresses may surface. Hence an understanding of the development, effects and possible avoidance of residual stress is vital and even more important for the semi-conductor industries as it goes into the nanometer technology. Whether process-induced, residual stress is a significant factor in high wafer breakage rates during microelectronic fabrication. Identifying the cause and initiation point of brittle fracture in processed wafers is an important first step towards the goal of making this and other newer technologies based on silicon commercially competitive. Infrared Phase Shift Gray Field which has showed some promises on residual stress measurement on silicon devices ranging from microelectronics to photovoltaic industry will be employed and developed. This method is based on the well known photoelastic principles, where the stress variations are measured based on the changes of light propagation velocity in birefringence material. In this research, the residual stress patterns that are not visible via conventional infrared transmission method will be used to locate defects. The magnitude of the residual stress fields associated with each defect is examined qualitatively and quantitatively. Firstly, the inspection of defects on wafer surface in early stage of wafer fabrication processes will be carried out. Next, an investigation of trapped particles and defects in bonded wafer with using the associated residual stress field will be also be covered.

Raytheon Visions Systems (RVS) is furthering its capability to deliver state-of-the-art high performance large format HgCdTe focal plane arrays (FPAs) for dual-band long-wavelength infrared (LWIR) detection. Missile seekers are designed to acquire targets of interest at long ranges and discriminate targets from clutter. The use of dual-band long wavelength infrared detector technology provides the ability for these seekers to combine these operations into the same package with enhanced performance. Increasing the format size of dual-band longwavelength FPAs and tailoring the detector design for specific long-wavelength bands enables seekers to be designed for increased field-of-view, longer target acquisition ranges, and improved accuracy. This paper will review in further detail the aspects of detector design, MBE wafer growth, wafer fabrication, and detector characterization that are contributing to development and demonstration of high performance large format dual-band LWIR FPAs at RVS.

Mask set price is soaring along with technology node advancement. One reason is that the number of masks per set is increasing with the geometry scaling. Another reason is that low k1 lithography with highly complex OPCs tightens dimensional mask specifications as to result in higher mask-making tool costs and lower production yield. Under these circumstances, tool cost reduction and production yield improvement are immensely required to reduce mask cost. Expensive quality-assured tools are indispensable to achieve the desired accuracy. Then, higher throughput and technical applicability of the same tool over multiple generations are definitely needed to improve total tool CoO. Meanwhile, not only such conventional basic approaches as improving field level and process performance but optimizing mask specifications efficiently is emerging as a key factor for keeping mask production yield high. Usually mask specifications are determined by the error budget allocated from the total lithography budget. In order to cope with the tighter specifications some sensible approaches have recently been proposed. Mask DFM is receiving particular attention as a new method being strongly linked to lithography and wafer fabrication technologies (1)(2)(3)(4). In this presentation, logical way to define the main mask specifications such as CD, defect and image placement accuracy is shown and sensible ways to sustain them are referred.

Two aspects are critical when a new reticle type is introduced in a wafer fab: printability and reticle inspection. In this study, we inspected 4 PSM reticles at the 45nm technology node, at P90, on the 5xx TeraScanHR platform. We successfully inspected SL2+ reticles of the PSM type at P90. We forecast that in a high volume 32nm node production environment, P72 SL2+ will address the inspectability challenges associated with PSM masks. This is based on strict requirements for sensitivity on contamination defects, inspectability, and cost of ownership, as when UMC addressed their wafer printability issues.

KLA-Tencor has introduced the new TeraFab reticle inspection systems for wafer fabs to address market demand for systems with high productivity and high sensitivity. The core inspection technology of the TeraFab systems is STARlight2+ (SL2+). STARlight is the industry accepted method for mask inspection in wafer fabs for reticle requalification. STARlight uses transmitted and reflected light images of a reticle to generate reference images of the reticle that are used to detect defects that have been added to the reticle while the reticle has was exposed or in storage. The improvements in reference generation in SL2+ relative to previous generations of STARlight is made possible, in part, by increases in computation resources for TeraFab systems. Improved modeling capability of SL2+ leads to increased usable sensitivity in dense geometries. Improved modeling capability also allows the user to optimize inspection cost of ownership (COO) if the maximum sensitivity of the TeraFab system is not required for a specific application. This paper describes an investigation of sensitivity versus throughput using SL2+ on multi-die production reticles with haze at the 65nm technology node. SL2+ data is also provided showing the feasibility of using larger inspection pixels (pixel migration) while retaining good sensitivity at the 45nm technology node.

As the industry embarks on sub 50nm half pitch design nodes, higher resolution and advanced inspection algorithm are needed to resolve shrinking features and find critical yield limited defects. In this paper, we evaluate the detection capability of STARlight2+ 72nm pixel on DRAM masks. The mask sets targeted for this evaluation were focused on critical layers. Although memory mask sets are dominated by multi-die layout, single die layout masks were also inspected because of their significance during research and development. Inspection results demonstrated the performance of STARlight2+ based on its sensitivity to contamination defects, inspectability, first time success rate and throughput. STARlight2+ has single die inspection capability, which is also needed in order to inspect scribe-lines and frame areas. The primary defects of interest are photo induced defects or contamination, causing mask degradation. Contamination continues to be the primary reason for mask returns at 193nm exposure across the industry. The objective of this paper is to demonstrate STARlight2+ 72nm capability to support memory wafer fab mask qualification requirements.

Lithographic process steps used in today's integrated circuit production require tight control of critical dimensions (CD). With new design rules dropping to 32 nm and emerging double patterning processes, parameters that were of secondary importance in previous technology generations have now become determining for the overall CD budget in the wafer fab. One of these key parameters is the intra-field mask CD uniformity (CDU) error, which is considered to consume an increasing portion of the overall CD budget for IC fabrication process. Consequently, it has become necessary to monitor and characterize CDU in both the maskshop and the wafer fab. Here, we describe the introduction of a new application for CDU monitoring into the mask making process at Samsung. The IntenCD TM application, developed by Applied Materials, is implemented on an aerial mask inspection tool. It uses transmission inspection data, which contains information about CD variation over the mask, to create a dense yet accurate CDU map of the whole mask. This CDU map is generated in parallel to the normal defect inspection run, thus adding minimal overhead to the regular inspection time. We present experimental data showing examples of mask induced CD variations from various sources such as geometry, transmission and phase variations. We show how these small variations were captured by IntenCD TM and demonstrate a high level of correlation between CD SEM analysis and IntenCD TM mapping of mask CDU. Finally, we suggest a scheme for integrating the IntenCD TM application as part of mask qualification procedure at maskshops.

This paper discusses the most efficient mask re-qualification inspection mode for 7Xnm half pitch design node production memory reticles in advanced memory wafer fab. By comparing overall performance including inspectability, sensitivity, and throughput for 8 different inspection modes, P150 Pixel Die-to-Die Reflected Light (P150 DDR) was identified to be the most desirable inspection mode for the specific use case where only one inspection mode is available. The evaluation was executed on the most critical layers - active, gate and contact layer. P150 DDR demonstrates the capability of providing early warning for the crystal growth type defects on both quartz and MoSi surfaces. It also showed good sensitivity for capturing small contamination defects in the dense Line/Space or Contact/Hole pattern areas. With a fast inspection scan speed and easy to use set up, TeraScanHR P150 DDR offers the best cost of ownership among all inspection modes. To gain higher sensitivity for smaller design nodes, TeraScanHR P150 DDR can be easily extended to smaller inspection pixels with minimum impact on productivity.

This paper proposes new scanner fleet management utilizing programmed hotspot patterns. We have developed a methodology to control and adjust critical parameters of scanner, such as effective illumination shape and numerical aperture (NA), to obtain the same lithography performance. The purpose is to improve hotspot patterns and depth of focus (DOF) of each scanner. The method is carried out with a test mask having programmed hotspot patterns that are likely to become fatal errors for circuit reliability in wafer processing. Actual circuit patterns whose patterning fidelity is sensitive to the critical parameters are selected as the programmed hotspots. The mask also has various lithography process monitor marks, such as flare monitor pattern, MEF evaluation pattern and aberration monitor pattern, for OPE control and simulation. Using the same test mask for every scanner, we can reveal the variation of lithography performance within a "scanner fleet". The hotspot patterns on the mask and the patterns printed onto wafers are inspected by Die-to-Database (D2DB) EB inspection and a wafer D2DB EB inspection, respectively. Using those D2DB inspection systems, we can evaluate quantitatively the change of pattern shape from drawing data to wafer. The OPE adjustment and OPC feedback are corrected by using the simulation data acquired for the D2DB inspection. The quality of the evaluation provides accurate scanner fleet control, resulting in high productivity and cost effectiveness at wafer fabrication.

Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of ≤ 1.5nm has been proposed. Reticle based measurements have shown that this proposed target can be met for standard overlay features and dedicated DPT features. In this paper we will present experimental intra field overlay wafer data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.

Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k 1 factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas TM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.

Reticle quality control in wafer fabs is different from quality control in mask shops. Mask shop requirements are typically inspectability of mask-type, resolution and sensitivity, with the latter usually being the most important. Mask shop sensitivity requirements are also fairly absolute. All defects or imperfections of a certain specification have to be found 100 percent of the time, every time. Wafer fab requirements are an interplay between inspectability, sensitivity, and the economic cost of inspection versus the economic risk of not inspecting. Early warning and defect signatures versus absolute capture of all defects is a key distinction between wafer fabs and mask shops. In order to better understand the different strategies and approaches taken by wafer fabs for reticle quality control an industry-wide benchmark survey of leading wafer fabs was undertaken. This paper summarizes the results while retaining the different wafer fabs' anonymity and confidentiality. The approach taken for the survey was specifically designed to be impartial and independent of any tools, solutions or applications available from KLA-Tencor.

The AIMS (Aerial Image Measurement Tool) measures approximate aerial images to scanner results by adjusting the numerical aperture, illumination type and partial parameters. Accordingly, AIMS tool is used generally to verify the issue points during manufacturing a mask. Normally using a mask for photolithography needs twice verifications. One is the qualification in the mask shop. The other is verification over the photo process using the mask in the wafer fab. If evaluated data at AIMS can be trusted about photo process ability including energy latitude (EL), depth of focus (DOF), CD uniformity (CDU), pattern fidelity and mask defects including repair area, AIMS can function as a first filter before shipping the mask. That means the AIMS data can be used as a preliminary data in the wafer fab. So this study is focused on correlation between measured data at AIMS fab 193i and ArF scanner over the photo process such as EL, DOF, CDU, pattern fidelity and mask defects. First, various patterns are made on attenuated PSM from 80 to 65nm tech. Next correlations are calculated about EL, DOF and CDU by using same optical conditions, measurement points and etc at AIMS and Scanner. Also the aerial images from AIMS are compared with scanner results on defective side how those are matched with each other. Consequently defect printability and CDU map at AIMS were similar to the scanner. In CDU point of view, AIMS exceeds the predictive ability of the mask CD SEM. Moreover it means that wafer CDU can be corrected (improved) independently on the CDU result of the wafer fab by using CDU correctable femto laser tool which reduces transmittance of the mask. Surprisingly, it is possible. And Aerial image about mask defects including repair area is useful to predict the problem of the mask, since it is similar to wafer results. But aerial image compared with wafer image has more difference at 65nm technology node than at 80nm. If adjustment of threshold or measuring method can be done, prediction of the scanner result will have no matter. In conclusion, predictive results at AIMS over photo process can be applied as a preliminary data and it can be used to another index verifying the mask quality.

Double patterning (DPT) lithography is seen industry-wide as an intermediate solution for the 32nm node if high index immersion as well as extreme ultraviolet lithography are not ready for a timely release for production. Apart from the obvious drawbacks of additional exposure, processing steps and the resulting reduced throughput, DPT possesses a number of additional technical challenges. This relates to, e.g., exposure tool capability, the actual applied process in the wafer fab but also to mask performance and metrology. In this paper we will address the mask performance. To characterize the mask performance in an actual DPT process, conventional parameters need to be re-evaluated. Furthermore new parameters might be more suitable to describe mask capability. This refers to, e.g., reticle to reticle overlay but also to CD differences between masks of a DPT reticle set. A DPT target of reticle to reticle induced overlay of 6nm, 3σ at mask level was proposed recently for the 32nm node. The results show that this target can be met. Besides that, local CD variations and local displacement become critical. Finally, the actual mask metrology for determination of these parameters might not be trivial and needs to be set up and characterized properly. In this paper we report on the performance of two-reticle sets based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. In a first step we focus on reticle to reticle overlay. The overlay between two masks evaluated for different wafer overlay targets is compared with measurements on actual resolution structures. In a second step, mask to mask CD variations are addressed. Off-target CD differences as well as variations of CD signatures on both reticles of a set are investigated. Finally, local CD variations and local displacements are examined. To this aim, local variations of adjacent structures on the reticle are characterized. The contribution of local effects to the overall CD and registration budget is estimated.

Advanced photonic devices and systems typically include electronic components for signal transduction, signal processing, and actuation. Mature and stable silicon microfabrication technologies offer a generous menu of options for building application-specific integrated circuits (ASICs) for reasonable dollar costs. An ASIC device can compress complex electronic functions into a single silicon chip, greatly reducing the size and mass of the electronic portion of the system. We discuss the use of mature-technology silicon ASICs for electronic interface to cutting-edge-technology optical sensors and actuators, including considerations of how the space environment impacts the ASIC design, and noting the interesting fact that consideration of silicon area is nearly irrelevant to the present-day economics of low-volume ASIC fabrication.

Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

Silex Microsystems handles a wide range of customized MEMS components. This speech will be describing Silex's MEMS foundry work model for providing customized solutions based on MEMS in a cost effective and well controlled manner. Factors for success are the capabilities to reformulate a customer product concept to manufacturing processes in the wafer fab, using standard process modules and production equipment. A well-controlled system increases the likelihood of a first batch success and enables fast ramp-up into volume production. The following success factors can be listed: strong enduring relationships with the customers; highly qualified well-experienced specialists working close with the customer; process solutions and building blocks ready to use out of a library; addressing manufacturing issues in the early design phase; in-house know how to meet demands for volume manufacturing; access to a wafer fab with high capacity, good organization, high availability of equipment, and short lead times; process development done in the manufacturing environment using production equipment for easy ramp-up to volume production. The article covers a method of working to address these factors: to have a long and enduring relationships with customers utilizing MEMS expertise and working close with customers, to translate their product ideas to MEMS components; to have stable process solutions for features such as Low ohmic vias, Spiked electrodes, Cantilevers, Silicon optical mirrors, Micro needles, etc, which can be used and modified for the customer needs; to use a structured development and design methodology in order to handle hundreds of process modules, and setting up standard run sheets. It is also very important to do real time process development in the manufacturing line. It minimizes the lead-time for the ramp-up of production; to have access to a state of the art Wafer Fab which is well organized, controlled and flexible, with high capacity and short lead-time for prototypes. It is crucial to have intimate control of processes, equipment, organization, production flow control and WIP. This has been addressed by using a fully computerized control and reporting system.

Critical dimension (CD) metrology is an important process step within the wafer fab. Knowledge of the CD values at resist level provides a reliable mechanism for the prediction of device performance. Ultimately tolerances of device electrical performance drive the wafer linewidth specifications of the lithography group. Staying within this budget is influenced mainly by the scanner settings, resist process and photomask quality. At the 65nm node the ITRS roadmap calls for sub-3nm photomask CD uniformity to support a sub-3nm wafer level CD uniformity. Meeting these targets has proven to be a challenge. What can be inferred from these specifications is that photomask level CD performance is the direct contributor to wafer level CD performance. With respect to phase shift masks, criteria such as phase and transmission control are also tightened with each technology node. A comprehensive study is presented supporting the use of photomask aerial image emulation CD metrology to predict wafer level Across Chip Linewidth Variation (ACLV). Using the aerial image can provide more accurate wafer level prediction because it inherently includes all contributors to image formation such as the physical CD, phase, transmission, sidewall angle, and other material properties. Aerial images from different photomask types were captured to provide across chip CD values. Aerial image measurements were completed using an AIMSTMfab193i with its through-pellicle data acquisition capability including the Global CDU MapTM software option for AIMSTM tools. The through-pellicle data acquisition capability is an essential prerequisite for capturing final CD data (after final clean and pellicle mounting) before the photomask ships or for re-qualification at the wafer fab. Data was also collected on these photomasks using a conventional CD-SEM metrology system with the pellicles removed. A comparison was then made to wafer prints demonstrating the benefit of using aerial image CD metrology.

In the semiconductor industry, control of ammonia at the parts-per-billion concentration level is critical to insure the integrity of the lithography process. Ammonia is emitted into wafer fab air by various semiconductor processes including CVD, wafer cleaning, coater tracks, and CMP, as well as from outdoor air. Exposure to even low parts-per-billion concentrations of ammonia during the photolithography process can lead to yield loss and unscheduled equipment downtime. Picarro, Inc. has developed a field-deployable, real time, ambient gas analyzer capable of continuously monitoring parts-per-trillion levels of ammonia in situ, and in real-time, thereby allowing a user to directly monitor ammonia levels in sensitive photo-lithography equipment.

High resolution mask inspection in advanced wafer fabs is a necessity. Initial and progressive mask defect problem still remains an industry wide mask reliability issue. Defect incidences and its criticality vary significantly among the type of masks, technology node and layer, fab environment and mask usage. A usage and layer based qualification strategy for masks in production need to be adopted in wafer fabs. With the help of a high-resolution direct reticle inspection, early detection of critical and also non-critical defects at high capture rates is possible. A high-resolution inspection that is capable of providing necessary sensitivity to critical emerging defects (near edge) is very important in advanced nodes. At the same time, a way to disposition (make a go / no-go decision) on these defective masks is also very important. As the impact of these defects will depend on not only their size, but also on their transmission and MEEF, various defect types and characteristics have to be considered. In this technical report the adoption of such a high-resolution mask inspection system in wafer fab production is presented and discussed. Data on this work will include inspection results from advanced masks, layer and product based inspection pixel assignment, defect disposition and overall wafer fab strategies in day-to-day production towards mask inspection.