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EUV lithography is expected to be inserted for the 32 nm node and extended for the 22 nm and below. Phase shift masks (PSM) are evaluated as a possible option to push the resolution limit of the Extreme Ultra violet lithography. This paper will focus on designs and measurements of PSM implemented by etching into the Mo/Si multilayer (ML). The design and the technological developments to elaborate PSM by etching is described. Phase shift Sample (PSS) have been carried out to calibrate in "true operating conditions", i.e. through the measurement of the phase shift they produce on a reflected wavefront, at the wavelength (λ=13.5nm). The method of calibration have been investigated with a Fresnel bimirror interferometer installed on the PSI Swiss Light Source Synchrotron to measure directly the value of interest, i.e the optical phase.

In the field of microelectronics, the Extreme Ultraviolet (EUV) lithography operating at λ=13,5 nm, appears, today, as the most promising future technology. The viability of this next generation technology has, however, to face several technical issues. Among them, the realisation of highly reflective EUV mirrors is one of the key issues and concerns the mirrors for light transport as well as the lithography masks. In this last case, the mirrors which consist in a periodic Mo/Si multi-layer coating deposited by ion beam sputtering suffer from reflectance limitations and thermal instabilities. In this paper, an experimental investigation on IBS deposited Mo/Si multi-layers is presented. The study is mainly focused on the formation of Mo/Si interfacial zones and their evolution with thermal annealing up to 600°C. Detailed investigations by high-resolution transmission electron microscopy (HRTEM) and energy filtering TEM have been performed in association with differential scanning calorimetric (DSC) analyses. For the purpose, dedicated samples were prepared enabling the identification of phase transformations occurring during thermal annealing. It will be shown, in particular, how this coupled characterisation approach (TEM+DSC) can help understanding the interface growth in such metal/silicon systems. The characterisation results are presented and discussed.

In this paper, defect counting results are presented both on silicon substrates and on EUV mask blanks with their equivalent PSL size distribution. The measurements are achieved with our counting defect prototype COMNET but also with a commercial tool. Improvements of COMNET have been performed to reach sensitivities (PSL equivalent size on silicon) of 80 nm on silicon substrate, 90 nm on EUV mask blank and 125 nm on glass substrate. A first analysis about COMNET repeatability is presented and the impacts of known errors on defect number and size values are evaluated. Typical counting data measured on a EUV mask blank having an added defect density inferior to 1 def/cm2 (defect size superior to 90 nm) are presented. The analysis of these data shows two main populations of added defects which are characteristic of the deposition process: one close to 100 nm and the other in the micron range. Each group represents half of the total number of added defects. The origins of these defects are finally discussed on the basis of specific experiments chosen to highlight the possible role of the different process steps.