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Through-silicon via (TSV) technology is a key feature for 3D circuit integration. TSVs are formed by etching a vertical via and filling them with a conductive material for creation of interconnections which go through the silicon or silicon-on-insulator (SOI) wafer. The Bosch etch process on Deep Reactive Ion Etching (DRIE) is commonly used for this purpose. The etch profile defined by the critical dimensions (CDs) at the top and at the bottom, by the depth and by the scallop size on the sidewall needs to be monitored and well controlled. In this work a nondestructive 3D metrology of deeply-etched structures with an aspect ratio of more than 10 and patterns with lateral dimensions from 2 to 7 μm in SOI wafer is proposed. Spectroscopic reflectometry in the spectral range of 250-800 nm using a production metrology tool was applied. The depth determinations based on different algorithms are compared. The Pearson correlation coefficient between measured and calculated reflection is suggested as the most appropriate method. A simple method for top CD evaluation is proposed by the measurement of reflection and using the polynomial approximation of reflection versus TSV filling coefficient which is determined as ratio of CD to pitch. The 3D RCWA simulations confirm this dependence.

Driven by new applications such as BiCMOS embedded RF-MEMS, high-Q passives, Si-based microfluidics for bio sensing and InP-Si BiCMOS heterointegration [1-4], accurate alignment between back and front side is highly desired. In this paper, we present an advanced back to front side alignment technique and implementation of it into the back side processing module of IHP’s 0.25/0.13 μm high performance SiGe:C BiCMOS technology. Using the Nikon i-line Stepper NSR-SF150, a new infrared alignment system has been introduced. The developed technique enables a high resolution and accurate lithography on the back side of the BiCMOS-processed Si wafers for additional backside processing, such as backside routing metallization. In comparison to previous work [5] with overlay values of 500 nm and the requirement of two-step lithography, the new approach provides significant improvement in the overlay accuracy with overlay values of 200 nm and a significant increase of the fabrication throughput by eliminating the need of the two-step lithography. The new non-contact alignment procedure allows a direct back to front side alignment using any front side alignment mark (Fig. 2), which generated a signal by reflecting the IR light beam. Followed by a measurement of the misalignment between both front to back side overlay marks (Fig. 3) using EVG®NT40 automated measurement system, a final lithography process with wafer interfield corrections is applied to obtain a minimum overlay of 200 nm. For the specific application of deep Si etching using Bosch process, the etch profile angle deviation across the wafer (tilting) has to be considered as well. From experimental data, an etch profile angle deviation of 8 μm across the wafer has been measured (Fig. 7). The overlay error caused by tilting was corrected by optimization and adjustment of the stepper offset parameters. All measurements of back to front side misalignment were performed with the EVG®40NT automated measurement system whereas the deep etch tilting errors were measured with an optical microscope using special vernier scales embedded in the backend-of-line metallization layer (Fig 4 and Fig. 5) of the IHP’s 0.25/0.13 μm SiGe:C BiCMOS technology. By applying the proposed method of back to front side alignment using infrared illumination alignment, the accuracy of backside fabrication processes like deep Si etching can be significantly improved. The developed technique is very promising to shrink the dimensions by minimizing the back to front side misalignment to improve the device performance of backside integrated components and technologies.

The application of Double Exposure Lithography (DEL) would enlarge the capability of 248 nm exposure technique to smaller pitch. We will use the DEL for the integration of critical layers for dedicated applications requiring resolution enhancement into 0.13 μm BiCMOS technology. In this paper we present the overlay precision and the focus difference of 1st and 2nd exposure as critical parameters of the DEL for k1 ≤ 0.3 lithography (100 nm half pitch) with binary masks (BIM). The realization of excellent overlay (OVL) accuracy is a main key of double exposure and double patterning techniques. We show the DEL requires primarily a good mask registration, when the wafer stays in the scanner for both exposures without alignment between 1st and 2nd exposure. The exposure tool overlay error is more a practical limit for double patterning lithography (DPL). Hence we prefer the DEL for the resolution enhancement, especially if we use the KrF high NA lithography tool for 130 nm generation. Experimental and simulated results show that the critical dimension uniformity (CDU) depends strongly on the overlay precision. The DEL results show CDU is not only affected by the OVL but also by an optical proximity effect of 1st and 2nd exposure and the mask registration. The CD uniformity of DEL demands a low focus difference between 1st and 2nd exposure and therefore requires a good focus repeatability of the exposure tool. The Depth of Focus (DOF) of 490 nm at stable CD of lines was achieved for DEL. If we change the focus of one of the exposures the CD-focus performance of spaces was reduced with simultaneous line position changing. CDU vs. focus difference between 1st and 2nd exposure demands a focus repeatability