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This paper extends the state of the art by demonstrating performance improvements in the Domain Decomposition Method (DDM) from a physical perturbation of the input mask geometry. Results from four testcases demonstrate that small, direct modifications in the input mask stack slope and edge location can result in model calibration and verification accuracy benefit of up to 30%. All final mask optimization results from this approach are shown to be valid within measurement accuracy of the dimensions expected from manufacture. We highlight the benefits of a more accurate description of the 3D EMF near field with crosstalk in model calibration and impact as a function of mask dimensions. The result is a useful technique to align DDM mask model accuracy with physical mask dimensions and scattering via model calibration.

Source-mask optimization (SMO) in optical lithography has in recent years been the subject of increased exploration as an enabler of 22/20nm and beyond technology nodes [1-6]. It has been shown that intensive optimization of the fundamental degrees of freedom in the optical system allows for the creation of non-intuitive solutions in both the source and mask, which yields improved lithographic performance. This paper will demonstrate the value of SMO software in resolution enhancement techniques (RETs). Major benefits of SMO include improved through-pitch performance, the possibility of avoiding double exposure, and superior performance on two dimensional (2D) features. The benefits from only optimized source, only optimized mask, and both source and mask optimized together will be demonstrated. Furthermore, we leverage the benefits from intensively optimized masks to solve large array problems in memory use models (MUMs). Mask synthesis and data prep flows were developed to incorporate the usage of SMO, including both RETs and MUMs, in several critical layers during 22/20nm technology node development. Experimental assessment will be presented to demonstrate the benefits achieved by using SMO during 22/20nm node development.

This paper presents our recent observations on variations in properties and damp heat (DH)-induced degradation behavior for single-layer 2%Al-doped ZnO (AZO) and bilayer ZnO (BZO), which comprises 0.1-μm intrinsic ZnO (i-ZnO) and AZO, deposited on glass substrates using the same sputtering system and essentially identical deposition conditions. BZO films with 0.12-μm AZO have been used on the National Renewable Energy Laboratory's (NREL's) high-efficiency CuInGaSe 2 (CIGS) solar cells for years. For the as-deposited BZO films, the most apparent variations appeared in notable peak shift in transmittance and reflectance spectra and ZnO (002) peak intensity and peak position in X-ray diffraction. Location of substrates placed on the substrate holder platform contributed partly to the variations. For the DH-degraded AZO and BZO, earlier films became highly resistive, porous, and 10~20 X thicker and showed flattened transmittance spectra caused by a loss of free-carrier absorption. However, recent DH-exposed AZO and BZO films also became highly resistive but exhibited only small changes in transmittance spectra, while the columnar grain structure and film thickness remained nearly unchanged without porous features, but with granular particles formed on the surfaces that increased in size with lengthening DH exposure time.

The topography effect of Opaque MoSi on Glass (OMOG) mask on 32nm contact hole patterning is analyzed by examining the difference of image intensity profile between thin mask approximation and rigorous electro-magnetic field (EMF) simulation. The study shows that OMOG topography results in more than a 20% decrease of image intensity. The impact of OMOG mask topography on lithography modeling of a 32nm contact hole process is explored by fitting lithography simulation with experimental results for both thin mask model and EMF model. This study shows that thin mask modeling is a good approximation of EMF modeling for a contact pitch larger than 120nm, but yields about 10nm prediction error for a 110nm contact pitch. Thin mask modeling is shown to be inaccurate in predicting critical dimension of contact arrays with sub-resolution assistant feature (SRAF). In addition, thin mask modeling is too pessimistic in predicting SRAF printability. In contrast, EMF model shows good prediction of contact arrays with and without sub-resolution feature. A modified thin mask modeling technique utilizing an effective SRAF size is proposed and verified with experimental results.

In this paper, we demonstrate a new methodology for post-etch OPC modeling to compensate for effects of underlayer seen on product wafers. Current resist-only OPC models based on data from flopdown wafers are not always accurate enough to deliver patterning solutions with stringent critical dimension requirements in 45/32nm technology node. Therefore it is necessary to include an etch model into the OPC correction. Both litho and etch model were built using flopdown and integrated wafers to compensate for topography, differential etch due to different underlayer substrate based on local geometry and local loading. The wafer data based on such OPC keyword show significant decrease of critical dimensions offsets of device macros from long poly-line nested structures for gate level. We will compare wafer data from two different OPC model versions built from flopdown and integrated wafer. We will also discuss modeling options in terms of two layer test masks for future technologies.

We present an etch-aware optical proximity correction (OPC) flow that is intended to optimize post-etch patterns on wafer. We take advantage of resource efficient empirical etch models and a model based retargeting scheme to determine post-develop in-plane resist targets required to achieve post-etch critical dimensions. The goal of this flow is to optimize final patterns on wafer rather than two independent patterns from lithography and etch. As part of this flow, we cover important aspects of etch process variability implications for etch aware OPC. Metrics for total pattern transfer are developed and explored with an eye toward optimizing pattern transfer. We present results from a 45 nm poly-silicon and 32 nm shallow trench isolation levels where etch aware OPC has been applied and compare these results with conventional resist based OPC schemes. Finally, implications of this flow for unit process developers in lithography and reactive ion etch are explored. We present a process optimization flow that incorporates model based retargeting into resolution enhancement technology selection, materials selection as well as lithographic and reactive ion etch process development.

Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently, the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful lithography-design optimization.

We review the fabrication process of a recently introduced phase only MEMS based spatial light modulators for maskless lithography. A brief description of this device is presented. The physical properties of its structural layers and the difficulties encountered during its fabrication process are described in detail.

Double exposure lithography processes can offer a significant yield enhancement for challenging circuit designs. Many decomposition techniques (i.e. the process of dividing the layout design into first and second exposures) are possible, but the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g. dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist features" or PrAFs) are designed to support the process window of critical features much like the role of the sub-resolution assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more design options, and hence a greater process exploration space, than are available for SRAFs. A decomposition scheme using PrAFs was developed for a gate level process. A critical driver of the work was to deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single-exposure process. A variety of PrAF techniques were investigated, including block type features, variable-pitch PrAFs, and constant assist-to-feature spacing (similar to SRAF placement). A PrAF scheme similar to standard SRAF rules was chosen as the optimal solution. The resulting ACLV benefits occurred mainly in the intermediate pitch range. For dense pitches, the ACLV was mostly unchanged, since in that regime neither process used assist features. The PrAF process showed a benefit of 10-44% improvement of ACLV in the mid-range pitches, but up to 18% worse ACLV for isolated pitches. Thus, the optimal double exposure solution was a combination of SRAFs and PrAFs that achieved the ACLV benefits of both.

Lithography simulation remains one of the primary aspects of most DfM flows, along with critical area analysis and chem-mech-polish (CMP) modeling. Often, the accuracy of the DfM flow is judged solely on the accuracy of the lithographic simulation. In this paper we attempt to refute that viewpoint and highlight the many sources of error in a DfM flow. We examine the factors that impact accuracy and attempt to quantify their effect. Differences between rigorous simulation, which includes full mask data preparation along with lithography simulation, and the use of compact models are explored. Required and achievable DfM accuracy over time and across multiple fabs is examined and the use of a "closed-loop" DfM flow is proposed.

For a robust OPC solution, it is important to isolate and characterize the detractors from high quality printability. Failure in correctly rendering the design intent in silicon can have multiple causes. Model inability in predicting lithographic and process implications is one of them. Process model accuracy is highly dependant on the quality of data used in the calibration phase of the model. Structures encountered during the OPC simulation that have not been included in the calibration patterns, or even structures somewhat similar to those used in calibration, are some times incorrectly predicted. In this paper a new method for studying VT5 model coverage during OPC simulations is investigated. The aerial image parameters for a large number of test structures used for model calibration are first calculated. A novel sorting and data indexing algorithm is then applied to classify the computed data into fast accessible look-up tables. These tables are loaded in the beginning of a new OPC simulation where they are used as a reference for comparing aerial image parameters calculated for new design fragments. Such new approach enables real time classification of design fragments based on how well covered they are by the VT5 model. Employing this method avoids catastrophic misses in the correction phase and allows for a robust approach to MBOPC.

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits manufactured with optical lithography technology. The accuracy of these models highly depends on the experimental data used in the model development and on the appropriate selection of the model parameters. The optical and resist model parameters selected during model build have a significant impact on the OPC model accuracy, run time, and stability. In order to avoid excessively high run times as well as ensure acceptable results, a compromise must be made between OPC run time and model accuracy. The modeling engineer has to optimize the necessary model parameters in order to find a good trade-off that achieves acceptable accuracy with reasonable run time. In this paper, we investigate the effect of some selected optical and resist model parameters on the OPC model accuracy, run time, and stability.

In recent years, design for manufacturability (DfM) has become an important focus item of the semiconductor industry and many new DfM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity and here we explore the role of through-process modeling on DfM applications. Several different DfM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored and methods to ensure their accuracy presented.

The need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. Three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. The importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. The need for extensive experimental calibration and improved simulation accuracy is also highlighted.

The impact of mask CD non-uniformity on the accuracy of optical proximity correction (OPC) models has been observed on several critical levels. In the current OPC model calibration flow, the mask effect is not explicitly separated from the optical and resist models. Instead, the resist model is compensating for the mask errors. In this paper, we report a detailed study of the effect of mask CD non-uniformity on OPC model accuracy using the established OPC model calibration flow. The influence of mask CD non-uniformity on the through process behavior of an OPC model is also discussed. A possible OPC flow to take the systematic mask CD error into consideration is proposed and a detailed study of mask modeling is present.

As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.

Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertainty's impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.

Membrane deformable mirror devices consist of a single large membrane that is suspended above an array of actuating electrodes. A transparent electrode is incorporated into the membrane mirror device in the optical path in an effort to provide significantly greater control of the membrane, and hence improved performance in an adaptive optics system. The devices presented here were fabricated from 1 mm thickness SOI; devices were bonded to electrode arrays with 1024 electrodes, packaged in ceramic pin grid arrays and driven by off chip D/A electronics. The transparent electrodes consist of glass that is ITO coated for electrical conductivity and visible light transmission. An electrode is inserted into a recessed cavity of each membrane chip, and is positioned 70 mm above the membrane. With 2x2 binned electrodes, the device demonstrates 10 mm deflection toward the electrode array at 40 V. Large deflection at low voltage is obtained because of the low intrinsic stress of the silicon membrane. These data also demonstrate modest deflection toward the transparent electrode, which may be improved with better alignment of the transparent electrode with the underlying membrane and electrode array in future devices.

As telecom networks increase in complexity there is a need for systems capable of manage numerous optical signals. Many of the channel-manipulation functions can be done more effectively in the optical domain. MEMS devices are especially well suited for this functions since they can offer large number of degrees of freedom in a limited space, thus providing high levels of optical integration. We have designed, fabricated and tested optical MEMS devices at the core of Optical Cross Connects, WDM spectrum equalizers and Optical Add-Drop multiplexors based on different fabrication technologies such as polySi surface micromachining, single crystal SOI and combination of both. We show specific examples of these devices, discussing design trade-offs, fabrication requirements and optical performance in each case.

We are developing membrane mirrors for use in adaptive optics, particularly in astronomy and vision science. We have micro-fabricated membrane mirrors from single crystal silicon using wet chemical etching and reactive ion etching. Membrane size, tension and operating voltage were selected to allow greater deformation of the mirror surface at low operating voltage than previous membrane mirror designs. Mirror devices consist of independently fabricated membrane and electrode array chips that are flip chip bonded together. We have fabricated electrode arrays with 256 and 1024 electrodes, and active diameters ranging from 6-10 mm (comparable to the size of the human pupil). Membrane-electrode hybrids are mounted to ceramic packages, wire bonded, and driven by off chip, D/A electronics. These devices are milestones in the development of an electret membrane mirror.

Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBM's early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

The line-width variation of a 193 nm lithographic process utilizing a 0.60 NA scanner and a binary reticle is compared to that of a 248 nm lithographic processes utilizing a 0.68 NA scanner and a variety of reticle technologies. These include binary, attenuated PSM with assist features and alternating PSM reticles. Despite the fact that the 193 nm tool has a lower NA and that the data was generated using a binary reticle, the 193 nm lithographic process allows for the line-width values to be pushed lower than previously achieved with 248 nm lithographic processes. The 3-sigma values from 4000 electrical linewidth measurements per wafer (160 measurements per 25*25 mm field, 25 fields per wafer) were calculated for different mask features. The 193 nm process was capable of reaching line-widths needed for future generations of advance logic chips. Compared to the 193 nm process utilizing a binary reticle, only the 248 nm processes utilizing either an attenuated PSM with assist features or an alternating PSM reticle had similarly low line-width variation. The 248 nm processes utilizing a binary reticle had higher line-width variation even at larger poly gate conductor line-widths.

Subresolution assist features, when used in conjunction with off-axis illumination, have shown great promise for reducing proximity effects while improving lithographic process window. However, these patterns result in an increased emphasis on the mask manufacturing process, primarily in the areas of mask writing and inspection. In choosing a design strategy, one must be careful to account for the mask making capabilities, such as write tool grid size and linearity, along with the lithographic effect of errors in the mask making process. In addition to mask errors, stepper lens aberrations and expected process variations can also have a large influence on design rules. Generally, design tradeoffs must be made to balance the impact of these for the best overall lithographic performance.

Characterization of line width variation by a three-step methodology is presented. Causes of line width variation with distinct spatial signatures are first isolated by spatial analysis. Sources with similar spatial signatures are then separated by contributor-specific measurements. Unanticipated components are lastly identified by examination of the residual from spatial analysis. Significant sources include photomask error, flare, aberrations, development non-uniformity, and scan direction asymmetry. These components are synthesized to quantify the contributions from the three modules of the patterning process: photomask, exposure system, and post-exposure processing. Although these modules are independent of one another their effects on line width variation may be correlated. Moreover, the relative contributions of the modules are found to vary with exposure tool, development track, and lithography strategy, affirming the usefulness of the methodology in process tracking and optimization.

The manufacturing implementation of alternating aperture PSM's (AltPSM) has been gated by the impacts these techniques have on reticle manufacturing, specifically reticle defect inspection and repair. Die-to-die inspection techniques have been achieved for some clearfield multiphase alternate phase reticles, but the required die-to-database solutions are not currently available with defect inspection systems. In response to these mask manufacturing issues and IC design layout issues, resolution enhancing techniques based on Darkfield Alternate Phase (DAP) reticle designs are now of growing importance. A DAP Programmed Evaluation Reticle, DAPPER, was fabricated and inspected on a new high numerical aperture ultraviolet reticle inspection system. The results show reasonable defect sensitivity performance in the presence of both reticle geometry and quartz etch topography characteristic of 130-nm node advanced logic circuit DAP reticles.

Multiple contact hole resist samples from a variety of DUV resist suppliers, including both acetal and ESCAP chemistries are evaluated on an organic anti-reflective under layer (ARC) using an attenuated phase shift mask (APSM). One sample exhibited excellent surface inhibition and superior lithographic performance for patterning contact holes of 0.2 micrometers imaging size. For most of resists, the process windows are limited by unwanted sidelobe printing through focus. The sensitivity of sidelobe printing to focus can be attributed to lens aberrations. For the first time, we prose to use Depth-of-focus (DOF) loss PWLdof and Exposure latitude (EL) loss PWLel to characterize resists surface inhibition, as well discovered that DOF loss is a sensitive measure of surface inhibition. Similar lithographic performance is obtained from acetal and ESCAP based materials. The two ESCAP resists EB3 and EA2 have better oxide etch resistance than the acetal resist AC1. The top surface reticulation is observed on ESCAP resist EB3 and EA2 during the oxide etch, but not on the acetal resist AC1. 110 nm underexposed resolutions achieved with the resist EA4 at a mask size of 250 nm. Faster resists generally exhibit better resolution but have smaller process windows when side lobe printing is included as a criterion. Selection of a resist formulation for attenuated phase shift applications has to face a compromise between resolution, photospeed, process window and surface inhibition. Finally, ARC operational modes and optical properties had little effect on sidelobe printing, and optimization of PEB temperature is important in suppressing sidelobe printing.

Magnification of mask dimensional error is examined and quantified in terms of the mask error factor (MEF) for line and hole patterns on three types of masks: chrome-on-glass (COG), attenuated phase-shifting mask (PSM) and alternating PSM. The MEF is unity for large features, but increases rapidly when the critical dimension (CD) is less than 0.5 (lambda) /NA for line-space patterns and 0.75 (lambda) /NA for contacts. In general dark-field spaces exhibit higher sensitivity to mask dimensional error than light-field lines. Sensitivity of attenuated PSMs is similar to COG masks, even for applications in which attenuated PSMs provide benefits in process latitude. Alternating PSMs have the lowest MEF values. Although the MEF has only a slight dependence on feature nesting for contacts, dense lines and spaces exhibit markedly higher MEF values than isolated features. The MEF of a 0.35 (lambda) /NA isolated line is 1.6 whereas that of a dense line of the same dimension is 4.3 illumination is effective in reducing the mask error sensitivity of dense lines. Dose variation causes changes in the MEF of contacts but has little effect on line-space features; focus error degrades (increases the value of) the MEF of both pattern types. A high diffusion and low contrast photoresist process also worsens the MEF. Consequences of mask CD error amplification include tightening of mask specification, design grid reduction, shift in optimal mask bias and enhanced defect printability.

The prerequisite to successful optical proximity correction is an in depth understanding of the relevant parameters leading to patterning inaccuracies. The work presented in this paper is based on a test chip specifically designed to investigate sources of 1D line width errors, deemed the most critical for optical proximity correction. Data are presented relating line width errors to pitch and pattern density and highlighting the complex interactions between these two main contributors of line width error. The goal of this paper is not to derive a mathematical model for line width variation in etched polysilicon line structures but merely to qualitatively bound the complex interaction of pitch and pattern density based line width variation. The results of this investigation indicate that pattern density has a very significant effect on line width and that lithography, not just reactive ion etch, is significantly impacted by pattern density.

As transistor features shrink into the deep submicron range, a corresponding reduction in the optical wavelength used to pattern such features has also continued. Currently, advanced optical steppers found in ULSI production applications operate at a wavelength of 365 nm with 248 nm optical lithography present in process development facilities and 193 nm lithography in the early stages of research. By reducing the wavelength still further to below 1.5 nm, x-ray lithography represents the ultimate limit of this paradigm. In this paper we present the experimental results of the first MOSFETs ever fabricated using a laser plasma-source x-ray stepper. These transistors were patterned using a mix-and-match lithography scheme where the gate level was printed using a 1.4 nm plasma-source x-ray stepper while the other layers were patterned using an optical stepper operating at a wavelength of 248 nm (DUV). The minimum gate length of these transistors is 0.12 micrometers with an effective channel length of 75 nm.

We have demonstrated a new type of near-field microscope that uses an add-on lens, called a solid immersion lens, to a real-time Nipkow disk type of confocal scanning optical microscope. Using this microscope, a factor of two improvement in the edge response over a confocal microscope has been observed along with excellent images of a grating with 100 nm strips and spaces. This microscope operates in reflection and gives real-time images.© (1992) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.