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The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated threedimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, IIIV, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the defectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.

The miniaturization of semiconductors continues, importance of overlay measurement is increasing. We measured overlay with analysis SEM called Miracle Eye which can output ultrahigh acceleration voltage in 1998. Meanwhile, since 2006, we have been working on SEM based overlay measurement and developed overlay measurement function of the same layer using CD-SEM. Then, we evaluated overlay of the same layer pattern after etching. This time, in order to measure overlay after lithography, we evaluated the see-through overlay using high voltage SEM CV5000 released in October 2016. In collaboration between imec and Hitachi High-Technologies, we evaluated repeatability, TIS of SEM-OVL as well as correlation between SEM-OVL and Opt-OVL in the M1@ADI and V0@ADI process. Repeatability and TIS results are reasonable and SEM-OVL has good correlation with Opt-OVL. By overlay measurement using CV 5000, we got the following conclusions. (1)SEM_OVL results of both M1 and V0 at ADI show good correlation to OPT_OVL. (2)High voltage SEM can prove the measurement capability of a small pattern(Less than 1~2um) like device that can be placed in-die area. (3)"In-die SEM based overlay" shows possibility for high order control of scanner

A methodology to evaluate the memory cell property of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) with a CD-SEM (Critical Dimension-Scanning Electron Microscope) was proposed. STTMRAM is one of the promising candidates among various emerging memories, owing to its low power consumption, low latency, and excellent endurance. Meanwhile, the major issues of STT-MRAM are its small resistance window and the etching-induced damage during memory pillar formation process. The resistance variability and the damage region should be minimized to achieve the reliable operation and the size scaling. The correlation analysis between the resistance and the physical dimension was performed. It provided quantitative information required for process development and control, such as the size-independent resistance variability, the width of the damaged region, and the origin of the short failures. They are essential for the investigation of the causes for the cell-to-cell resistance variability as well as for the quantification of the damage during etching process.

In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.

With the continuous shrink in pattern size and increased density, overlay control has become one of the most critical issues in semiconductor manufacturing. Recently, SEM based overlay of AEI (After Etch Inspection) wafer has been used for reference and optimization of optical overlay (both Image Based Overlay (IBO) and Diffraction Based Overlay (DBO)). Overlay measurement at AEI stage contributes monitor and forecast the yield after formation by etch and calibrate optical measurement tools. however those overlay value seems difficult directly for feedback to a scanner. Therefore, there is a clear need to have SEM based overlay measurements of ADI (After Develop Inspection) wafers in order to serve as reference for optical overlay and make necessary corrections before wafers go to etch. Furthermore, to make the corrections as accurate as possible, actual device like feature dimensions need to be measured post ADI. This device size measurement is very unique feature of CDSEM , which can be measured with smaller area. This is currently possible only with the CD-SEM. This device size measurement is very unique feature of CD-SEM , which can be measured with smaller area. In this study, we assess SEM based overlay measurement of ADI and AEI wafer by using a sample from an N10 process flow. First, we demonstrate SEM based overlay performance at AEI by using dual damascene process for Via 0 (V0) and metal 1 (M1) layer. We also discuss the overlay measurements between litho-etch-litho stages of a triple patterned M1 layer and double pattern V0. Second, to illustrate the complexities in image acquisition and measurement we will measure overlay between M1B resist and buried M1A-Hard mask trench. Finally, we will show how high accelerating voltage can detect buried pattern information by BSE (Back Scattering Electron). In this paper we discuss the merits of this method versus standard optical metrology based corrections.

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

A method of sub-nanometer uncertainty for the 3D-profile measurement using TEM (Transmission Electron Microscope) images is proposed to standardize 3D-profile measurement through reference metrology. The proposed method has been validated for profiles of Si lines, photoresist features and advanced-FinFET (Fin-shaped Field-Effect Transistor) features in our previous investigations. However, efficiency of 3D-profile measurement using TEM is limited by measurement time including processing of the sample. In this article, we demonstrate a novel on-wafer 3D-profile metrology as "FIB-to-CDSEM method" with FIB (Focused Ion Beam) slope cut and CD-SEM (Critical Dimension Secondary Electron Microscope) measuring. Using the method, a few micrometer wide on a wafer is coated and cut by 45 degree slope using FIB tool. Then, the wafer is transferred to CD-SEM to measure the cross section image by top down CD-SEM measurement. We apply FIB-to-CDSEM method to CMOS sensor device. 3D-profile and 3D-profile parameters such as top line width and side wall angles of CMOS sensor device are evaluated. The 3D-profile parameters also are measured by TEM images as reference metrology. We compare the 3D-profile parameters by TEM method and FIB-to-CDSEM method. The average values and correlations on the wafer are agreed well between TEM and FIB-to- CDSEM methods.

Line edge roughness (LER) and line width roughness (LWR) are analyzed during pattern transfer in a self-aligned quadruple patterning (SAQP) process. This patterning process leads to a final pitch of 22.5nm, relevant for N7/N5 technologies. Measurements performed by CD SEM (Critical Dimension Scanning Electron Microscope) using different settings in terms of averaging, field of view, and pixel size are compared with reference metrology performed by planar TEM and three-Dimensional Atomic Force Microscope (3D AFM) for each patterning process step in order to investigate the optimal condition for an in-line LWR characterization. Pattern wiggling is als0 quantitatively analyzed during LER/LWR transfer in the SAQP process.

A novel method of sub-nanometer uncertainty for the line profile measurement using TEM (Transmission Electron Microscope) images is proposed to calibrate CD-SEM (Critical Dimension Scanning Electron Microscope) line width measurement and to standardize line profile measurement through reference metrology. The proposed method has been validated for profile of Si line and photoresist features in our previous investigations. In this article, we apply the methodology to line profile measurements of advanced-FinFET (Fin-shaped Field-Effect Transistor) features. The FinFET features are sliced as thin specimens of 100 nm thickness by FIB (Focused Ion Beam) micro sampling system. Cross-sectional images of the specimens are obtained then by TEM. The profiles of fin, hardmask and dummy gate of FinFET features are evaluated using TEM images. The width of fin, the length of hardmask, and the length of dummy gate of FinFET features are measured and compared to CD-SEM measurement. The TEM results will be used to implement CD-SEM and CD-AFM reference metrology.

As EUV Lithography (EUVL) continues to evolve, it offers a possible solution to the problems of additional masks and lithography steps that drive up the cost and complexity of 193i multiple patterning. EUVL requires a non-telecentric reflective optical system for operation. This requirement causes EUV specific effects such as shadowing. The absorber physically shadows the reflective multilayer (ML) on an EUV reticle resulting in pattern fidelity degradation. To reduce this degradation, a thinner absorber may help. Yet, as the absorber thickness decreases, reflectivity increases in the ‘dark’ region around the image field, resulting in a loss of contrast. The region around the edge of the die on the mask of unpatterned absorber material deposited on top of ML, known as the image border, is also susceptible to undesirable reflections in an ideally dark region. For EUVL to be enabled for high-volume manufacturing (HVM), reticle masking (REMA) blades are used to shield light from the image border to allow for the printing of densely spaced die. When die are printed densely, the image border of each neighboring die will overlap with the edge of a given die resulting in an increase of dose that overexposes features at the edge of the field. This effect is convolved with a fingerprint from the edge of the REMA blades. This phenomenon will be referred to as a field edge effect. One such mitigation strategy that has been investigated to reduce the field edge effect is to fully remove the ML along the image border to ensure that no actinic-EUV radiation can be reflected onto neighboring die. This has proven to suppress the effect, but residual out-of-band radiation still provides additional dose to features near the image border, especially in the corners where three neighboring fields overlap. Measurements of dense contact holes (CHs) have been made along the image border with and without a ML-etched border at IMEC in collaboration with Micron using the ASML NXE:3100. The implementation of these measurements allow for further mitigation, i.e., compensation by OPC. Mentor Graphics’ Calibre software uses the scanner’s point spread function and convolves it with the mask layout to generate a flare map. It also has the capability to add additional dose to the image border which can be optimized to fit the experimental data. This includes the transition region between the image field and border that results in a linear rolloff of dose due to partial shadowing of the REMA blades. By applying this flaremap that accounts for neighboring die to the already calibrated optical and resist models, OPC can now be enabled to compensate for field edge effects. This study has two goals. First, we will show that OPC can be used to compensate both for field edge effects with and without a etched ML border. The second is to investigate the limitations that exist for OPC in the areas altered by neighboring die. This will predict when a process to mitigate the field edge effect is needed to enable EUV HVM.

Although extreme ultraviolet lithography (EUVL) remains a promising candidate for semiconductor device manufacturing of the 1x nm half pitch node and beyond, many technological burdens have to be overcome. The “field edge effect” in EUVL is one of them. The image border region of an EUV mask,also known as the “black border” (BB), reflects a few percent of the incident EUV light, resulting in a leakage of light into neighboring exposure fields, especially at the corner of the field where three adjacent exposures take place. This effect significantly impacts on CD uniformity (CDU) across the exposure field. To avoid this phenomenon, a light-shielding border is introduced by etching away the entire absorber and multi-layer (ML)at the image border region of the EUV mask. In this paper, we present a method of modeling the field edge effect (also called the BB effect) by using rigorous lithography simulation with a calibrated resist model. An additional “flare level” at the field edge is introduced on top of the exposure tool flare map to account for the BB effect. The parameters in this model include the reflectivity and the width of the BB, which are mainly determining the leakage of EUV light and its influence range, respectively. Another parameter is the transition width which represents the half shadow effect of the reticle masking blades. By setting the corresponding parameters, the simulation results match well the experimental results obtained at the imec’s NXE:3100 EUV exposure tool. Moreover, these results indicate that the out-of-band (OoB) radiation also contributes to the CDU. Using simulation we can also determine the OoB effect rigorouslyusing the methodology of an “effective mask blank”. The study in this paper demonstrates that the impact of BB and OoB effects on CDU can be well predicted by simulations.

Line width roughness remains a critical issue when moving towards smaller feature sizes in EUV lithography. We present a stochastic resist modeling approach to accurately predict LWR and CD simultaneously. The stochastic model simulates the roughness effects due to the shot noise and secondary electron effects during exposure, and the interaction amongst the finite number of chemical molecules (inhibitor, PAG, quencher) during PEB. The model calibration used the imec baseline EUV resist (Shinetsu SEVR140) with over 250 measured CDs and corresponding line width roughness data. The validation was performed with 1D and 2D patterns. Especially for contact holes the predictability regarding local CD uniformity is discussed. The good match between the simulations and wafer results for SRAM patterns further exhibits the predictive power of the model. The model has been applied to simulate the new ASML NXE: 3100 EUV conditions for both thin and thick absorber EUV masks. The comparison between the simulation results and wafer data are reported.

As Extreme Ultraviolet Lithography (EUVL) enters the pre-production phase, the need to qualify the Electronic Design Automation (EDA) infrastructure is pressing. In fact, it is clear that EUV will require optical proximity correction (OPC), having its introduction shifted to more advanced technology nodes. The introduction of off-axis illumination will enlarge the optical proximity effects, and EUV-specific effects such as flare and shadowing have to be fully integrated in the correction flow and tested. We have performed a model calibration exercise on the ASML NXE:3100 pre-production EUVL scanner using Brion's Tachyon NXE EUV system. A model calibration mask has been designed, manufactured and characterized. The mask has different flare levels, as well as model calibration structures through CDs and pitch. The flare modulation through the mask is obtained by varying tiling densities. The generation of full-chip flare maps has been qualified against experimental results. The model was set up and calibrated on an intermediate flare level, and validated in the full flare range. Wafer data have been collected and were used as input for model calibration and validation. Two-dimensional structures through CD and pitch were used for model calibration and verification. We discuss in detail the EUV model, and analyze its various components, with particular emphasis to EUV-specific phenomena such as flare and shadowing.

Extreme ultraviolet (EUV) - lithography at a wavelength around 13.5 nm is considered as the most promising successor of optical projection lithography. This paper reviews simulation models for EUV lithography. Resist model parameters are calibrated with experimental data. The models are applied for the investigation of the impact of mask multilayer defects on the lithographic process.

Extreme ultraviolet lithography (EUVL) sources emit a broad spectrum of wavelengths ranging from EUV to DUV and beyond. If the deep ultraviolet (DUV) reaches the wafer it will affect imaging performance by exposing the photoresist. Hence it is critical to determine the amount of DUV out of band (OoB) present in a EUVL tool, as well as its effect on the printed features on the wafer. In this study we investigate the effect of DUV OoB in EUVL. A model is developed in order to be able to quantify the DUV/EUV ratio at wafer level and all the required input parameters are estimated in the range from 140 to 400nm, as well as for the EUV at 13.5nm. The transmission of the optical system was estimated based on the optical design and reflectivity measurements of the mirrors. The mask reflectivity for multilayer (ML) and absorber was measured at wavelengths down to 140 nm and for EUV. The sensitivity to EUV and DUV for a variety of resist platforms was measured at 13.5 nm, 157 nm, 193 nm, 248 nm and 365 nm. The source spectra were also measured. By using these inputs, it was possible to estimate the DUV/EUV ratio for two different ASML tool configurations, the EUV Alpha Demo Tool and the NXE:3100. Both NXE:3100 with LPP (laser produced plasma) source and Alpha Demo Tool with DPP (discharge produced plasma) source show less than 1% DUV/EUV ratio in resist. The modeling predictions were compared to experimental results. A methodology is introduced to measure the DUV/EUV ratio at wafer level in situ. With this aim, an aluminum coated mask was fabricated and its reflectivity was qualified in both EUV and DUV wavelength range. By comparing the dose to clear exposures of a reflective blank and of the aluminum mask, it is possible to quantify the DUV/EUV ratio. The experimental results are in order of magnitude agreement with modeling predictions. The proposed experimental approach can be used to benchmark the DUV sensitivity of different resist platforms and may be used to monitor DUV OoB.

The introduction of EUV lithography into the semiconductor fabrication process will enable a continuation of Moore's law below the 22 nm technology node. EUV lithography will, however, introduce new and unwanted sources of patterning distortions which must be accurately modeled and corrected on the reticle. Flare caused by scattered light in the projection optics is expected to result in several nanometers of on-wafer dimensional variation, if left uncorrected. Previous work by the authors has focused on combinations of model-based and rules-based approaches to modeling and correction of flare in EUV lithography. Current work to be presented here focuses on the development of an all model-based approach to compensation of both flare and proximity effects in EUV lithography. The advantages of such an approach in terms of both model and OPC accuracy will be discussed. In addition, the authors will discuss the benefits and tradeoffs associated with hybrid OPC approaches which mix both rules-based and modelbased OPC. The tradeoffs to be explored include correction time, accuracy, and data volume.

EUV lithography is widely viewed as a main contending technology for 16nm node device patterning. However, EUV has several complex patterning issues which will need accurate compensation in mask synthesis development and production steps. The main issues are: high flare levels from optical element roughness, long range flare scattering distances, large mask topography, non-centered illumination axis leading to shadowing effects, new resist chemistries to model very accurately, and the need for full reticle optical proximity correction (OPC). Compensation strategies for these effects must integrate together to create final user flows which are easy to build and deploy with reasonable time and cost. Therefore, accuracy, usability, speed and cost are important with methods that have considerably more complexity than current optical lithography mask synthesis flows. In this paper we analyze the state of the art in accurate prediction and compensation of several of these complex EUV patterning issues, and compare that to 16nm node expected production needs. Next we provide a description of integration issues and solutions which are being implemented for 16nm EUV process development. This includes descriptions of OPC model calibration with flare, shadowing, and topography effects. We also propose a realistic (in terms of accuracy and mask area) flare parameter calibration flow to improve short and longer range flare correction accuracy above what can be achieved with only a measured EUV flare PSF.

In this paper, we discuss the performance of EUV resist models in terms of predictive accuracy, and we assess the readiness of the corresponding model calibration methodology. The study is done on an extensive OPC data set collected at IMEC for the ShinEtsu resist SEVR-59 on the ASML EUV Alpha Demo Tool (ADT), with the data set including more than thousand CD values. We address practical aspects such as the speed of calibration and selection of calibration patterns. The model is calibrated on 12 process window data series varying in pattern width (32, 36, 40 nm), orientation (H, V) and pitch (dense, isolated). The minimum measured feature size at nominal process condition is a 32 nm CD at a dense pitch of 64 nm. Mask metrology is applied to verify and eventually correct nominal width of the drawn CD. Cross-sectional SEM information is included in the calibration to tune the simulated resist loss and sidewall angle. The achieved calibration RMS is ~ 1.0 nm. We show what elements are important to obtain a well calibrated model. We discuss the impact of 3D mask effects on the Bossung tilt. We demonstrate that a correct representation of the flare level during the calibration is important to achieve a high predictability at various flare conditions. Although the model calibration is performed on a limited subset of the measurement data (one dimensional structures only), its accuracy is validated based on a large number of OPC patterns (at nominal dose and focus conditions) not included in the calibration; validation RMS results as small as 1 nm can be reached. Furthermore, we study the model's extendibility to two-dimensional end of line (EOL) structures. Finally, we correlate the experimentally observed fingerprint of the CD uniformity to a model, where EUV tool specific signatures are taken into account.

The switch from 193i to EUV Photolithography will bring some fundamental changes in exposure. The flare levels of an EUV machine are significantly higher compared with standard 193i machines. Moreover shadow effects on the reticle are not equivalent to 193i. It is inevitable that these fundamentals require modifications in the Optical Proximity Correction (OPC) flow. In this paper in collaboration with ASML BRION the critical enabling steps of the Mask Data Preparation (MDP) for EUVL, Flare, Shadowing and Optical and Process Corrections (OPC), are investigated. We measured the needs of the EUV MDP flow against the capabilities of a state-of-the art OPC flow built for 193i. Adaptations are being made to implement features which are currently not available in a 193i based flow. We present a feasibility study of the Model Based approach to the EUV OPC on a wide selection of features. Also we demonstrate simulations and verification of the EUV modeling capabilities of the TachyonTM with various levels and ranges of flare and prove the applicability of the reviewed approach to the process development for the 27nm EUV node.. We also evaluated the accuracy of the EUV OPC modeling and expected OPC corrections on the reviewed selection of clips as a substantial part of the overall CDU budget. Finally an overall EUV OPC flow as a manufacturable solution based on the Tachyon's predictions and ASML's knowledge of Photolithography was discussed.

One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.

Extreme Ultraviolet Lithography (EUVL) is the leading candidate beyond 32nm half-pitch device manufacturing. Having completed the installation of the ASML EUV full-field scanner, IMEC has a fully-integrated 300mm EUVL process line. Our current focus is on satisfying the specifications to produce real devices in our facilities. This paper reports on the imaging fingerprint of the EUV Alpha Demo Tool (ADT), detailing resolution, imaging, and overlay performance. Particular emphasis is given to small pitch contact holes, which are a critical layer for advanced manufacturing nodes and one of the most likely layers where EUVL may take over from 193nm lithography. Imaging of cont act holes, pattern transfer and successful pr inting of the contact hole level on a 32nm SRAM device is demonstrated. The impact of flare and shadowing on EUV ADT perf ormance is characterized experimentally, enabling the implementation of appropriate mitigation strategies. Keywords: EUV lithography, shadowing, flare.

EUV lithography is one of the hot candidates for the 22nm node. A well known phenomenon in EUV lithography is the impact of non-telecentricity and the mask topography on printing performance. Due to oblique illumination of the mask, layout, the printed features are shifted and biased on the wafer with respect to their target dimension up to several nanometers. This effect is inherent to EUV imaging systems. In order to maintain CDU, overlay and registration requirements, these effects need to be compensated for as part of the lithographic manufacturing process. Conventional compensation techniques, such as OPC compensation, significantly increase the complexity of the litho process. In this paper we discuss pattern shift, which is induced by mask-side non-telecentricity of the EUV ring field system. In particular, we show how the mask position relative to the focal plane of the projection system impacts pattern shift. It is shown that mask focus shift allows for a compensation of pattern shift, independent on angle of incidence, pattern type, pattern pitch, pattern orientation, and slit position. Thus it is seen that placement error is not an effect related to mask topography (not a shadowing effect) but arises purely from the mask non-telecentricity. A geometric interpretation of this effect is given and shown to be consistent with results of rigorous simulations. A method to simulate the shift of the mask focus position is briefly discussed. The mask focus shift for which the pattern shift vanishes in the aerial wafer image at best focus is determined using rigorous simulations. The amount of mask focus shift to compensate for the pattern shift is found to be approximately 136nm. This mask focus shift is then applied to investigate the through focus and dose behavior of the pattern shift in the resist. It is shown that the pattern shift is a function of wafer focus position and that this is a result of the image tilt in EUV systems. While the pattern shift is fully compensated at one wafer focus position, the shift at other positions is very small. The impact of the mask focus position on process window is investigated.

EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. This paper deals with the investigation of the impact of the mask blank architecture on the wafer print by EUV lithography. Presently the material stack on the mask is not fixed and different suppliers offer a range of variation. The purpose of the present paper is threefold, as detailed hereafter. First it is shown that there are possibilities to make EUV masks less prone to reflectivity loss by carbon contamination. An estimate is given for the required limitations on mask contamination and fabrication tolerance to keep the imaging impact below acceptable levels. These data can be used as preliminary error budgets for the individual and combined capping layer deterioration phenomena. Further-on, printing results on the Alpha Demo Tool (ADT) are reported, obtained with different reticles with identical layout produced on blanks with different mask stacks. In preparation for this experimental work simulations have been undertaken. The experimental results show good agreement in printing performance between the reticles tested. Finally, our work clearly shows the opportunity to reduce the absorber thickness without noticeable loss of contrast and with the big advantage of shadowing effect reduction.

A detailed defect printability analysis is reported for conditions that are fully representative for the world's first full field EUV scanner, using 4X reticles, as obtained by simulation. For absorber type defects the historical rule of thumb underestimates the printability. An opaque defect located in a space within a 40nm lines and space pattern can already cause more than a 10% change in the space width from 80% of the space width onwards (>32nm at mask scale, >8 nm at wafer scale) depending on its location. Absorber type clear defects start affecting line width in 40nm lines and spaces from about twice the size of an opaque defect. Particles simulated as carbon cubes have a similar effect as absorber type opaque defects provided that they are about 50% larger. Other possible particle materials are investigated as well. Local carbon deposition, which may originate from SEM inspection, can cause a printing effect already at a thickness of only 2nm. Multilayer or substrate type defects require surface smoothing to less than about 2nm, as to keep the impact of so-called phase defects under control. Experimental plans for comparison of simulations to exposures on the ASML Alpha Demo Tool installed at IMEC are included.

A research program on EUV lithography has been started at IMEC, based on ASMLs EUV full field scanner, the Alpha Demo Tool (ADT). It contains three main projects: EUV resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and establish the necessary mask and resist infrastructure, and achieve learning to prepare for the use of EUV lithography in future production of integrated circuits. Good progress in resist performance, as assessed by interference lithography, is illustrated by the ability of some materials to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of a defect printability assessment by simulation and a study of blank reflectivity control. Guidance is given to the EUV mask infrastructure to assure timely availability of reticles, first for the alpha demo tool (ADT), but also in preparation for future use of EUV lithography in production. In the ADT assessment project, simulation studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects are well understood Strategies for flare mitigation and shadowing effect correction are proposed.

As device critical dimensions (CD) decrease, they approach the limits of standard metrology techniques and measuring features smaller than 20 nm represents a serious challenge. Within the framework of the 32 nm program at IMEC, a reliable and accurate approach to small feature metrology is required. We describe here a methodology aimed at measuring features down to 10nm by means of scatterometry. The results are compared to calibrated CDSEM measurements [1]. The active fins of a Multi Gate Field Effect Transistors (MuGFET) was measured across wafer and across batch. Scribe to cell correlation, wafer fingerprint, 3D profile, oxide thickness were also investigated. In particular, 3D profile information was compared to TEM. Our approach produced very consistent results for all measurement techniques (scatterometry, CDSEM and TEM) and it is now fully integrated in the IMEC production line to monitor the MuGFET platform.

CD-SEM is currently poised as the primary method of choice for CD metrology because of its nanometer scale spatial resolution, superior precision, and relatively high throughput. However, issues still continue to emerge that can threaten the measurement performance for the various sample types encountered. The impact of issues arising from electron beam induced modification of the sample materials on critical dimensional metrology and lithographic process control will be assessed and approaches to mitigate these effects will be proposed. The two primary issues of interest related to scanned electron beam based measurements of patterned lithographic materials in this article are shrinkage of the ArF 193nm resist and undesired deposition of contaminants occurring during CDSEM measurements.

As we move forward to the 45 and 32nm node, MuGFET's (Multi-Gate Field-Effect Transistor) are considered more and more as a necessary alternative to keep pace with Moore's Law. If proven manufacturable, MuGFET's could eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the application of design-based metrology (DBM) to MuGFET OPC validation.

Resolution enhancement techniques (RET), immersion lithography, and Design for Manufacturing (DFM) are all geared towards increasing the lithographic process window to enable the ever more difficult processing demands of semiconductor manufacturing. It is well understood that there is a trade-off between depth of focus (DOF) and exposure dose latitude (EL), as well as best focus (BF) and best exposure dose (BE), in which a Manufacturable Process Window (MPW) must be established and centered. Oftentimes it is overlooked that this balance needs to be maintained across multiple dimensions including spatial (e.g. across field), density (e.g. dense, iso), temporal, tool-to-tool, etc. To maintain this critical balance, both test wafers and product wafers need to be monitored and analyzed in order to support Advanced Process Control (APC) and Automated Equipment Control (AEC). In this work we establish a method to optimize process window by using an integrated analysis workstation based on measurements from both optical and e-beam metrology. By applying this method, we demonstrate a MPW on daily FEM and nominal wafers already used at IMEC for daily process qualification.