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In advanced technology nodes, layout regularity has become a mandatory prerequisite to create robust designs less sensitive to variations in manufacturing process in order to improve yield and minimizing electrical variability. In this paper we describe a method for designing regular full custom layouts based on design and process co-optimization. The method includes various design rule checks that can be used on-the-fly during leaf-cell layout development. We extract a Layout Regularity Index (LRI) from the layouts based on the jogs, alignments and pitches used in the design for any given metal layer. Regularity Index of a layout is the direct indicator of manufacturing yield and is used to compare the relative health of different layout blocks in terms of process friendliness. The method has been deployed for 28nm and 40nm technology nodes for Memory IP and is being extended to other IPs (IO, standard-cell). We have quantified the gain of layout regularity with the deployed method on printability and electrical characteristics by process-variation (PV) band simulation analysis and have achieved up-to 5nm reduction in PV band.

28nm metal 90nm pitch is one of the most challenging processes for computational lithography due to the resolution limit of DUV scanners and the variety of designs allowed by design rules. Classical two dimensional hotspot simulations and OPC correction isn’t sufficient to obtain required process windows for mass production. This paper shows how three dimensional resist effects like top loss and line end shortening have been calibrated and used during the OPC process in order to achieve larger process window. Yield results on 28FDSOI product have been used to benchmark and validate gain between classical OPC and R3D OPC.

From 28nm technology node and below, Optical Proximity Correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for implant layers. In this paper, we implement a sub-layer aware simulation method into a verification tool for Optical Rule Check (ORC) that is used on full 28nm test chip. The sub-layer aware verification can predict defects that are missed by standard ORC. SEM-CD review and defectivity analysis were used to confirm the validity of the sub-layer aware model on wafer.

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist [1]. This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning [2] [3]. For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.

With the decrease of the transistors dimensions, process steps usually considered as not critical become challenging. This is the case for implant levels patterning, which can be strongly impacted by reflections from the underlying active and gate patterns, especially when no anti-reflective coating can be used. This stack effect leads to unexpected resist shape on wafer if not taken into account during OPC flow. We propose a solution to integrate stack effect onto existing OPC models by adding fictive layers at mask level in order to allow a stack-aware OPC or mask verification. This method can be implemented in a standard OPC flow offered by EDA OPC software. It provides effective results compatible with production constrains, such as stack-aware full chip simulation and run time efficiency.

Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire field through process windows. LMC is catching and reporting weak lithographic points having small process windows or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters. ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at different field locations. In this study we compare such across-field LMC verification with a reference LMC without any scanner specific data. Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots or scanner drifts and compared with wafer measurement. Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the methodology on identified critical hot spots.

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.

The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these applications. The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust 28nm node and prepare for 20nm. These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print check, aka LFD, for 28nm P&R.

As the OPC scripts become more and more complex for advanced technology nodes, the number of parameters used to control the convergence increases drastically. This paper does not aim to determine what a "good convergence criteria" is but rather to review the efficiency of the existing OPC solutions in terms of accuracy and parameter dependence, to solve simple design layouts. Three different OPC solutions, including a "standard algorithm", a "local convergence OPC" and a more holistic OPC, are compared on a design containing lines and line-ends. A cost function is used to determine the quality of the convergence for each type of structure. A map of convergence (iteration vs OPC Option) will be deduced for each structure.

Double patterning (DP) is one of the main options to print devices with half pitch less than 45nm. The basis of DP is to decompose a design into two masks. In this work we focus on the decomposition of the contact pattern layer. Contacts with pitch less than a split pitch are assigned to opposite masks corresponding to different exposures. However, there exist contact pattern configurations for which features can not be assigned to opposite masks. Such contacts are flagged as color conflicts. With the help of design of manufacturing (DFM), the contact conflicts can be reduced through redesign. However, even the state of the art DFM redesign solution will be limited by area constraints and will introduce delays to the design flow. In this paper, we propose an optical method for contact conflicts treatment. We study the impact of the split on imaging by comparing inverse lithography technology (ILT), optical proximity correction (OPC) and source mask co-optimization (SMO) techniques. The ability of these methods to solve some split contacts conflicts in double patterning are presented.

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important mask writing time due to the shotcount 4. In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited. Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of DOF and Runtime performance for hole patterning

In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by creating a short-range mask process model (MPM) for each unique mask process and a long-range CD uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1) and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with the current results of this new dynamic application to improve hot spot verification through Brion Technologies' model-based mask verification loop.

The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.

One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model. The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing has become ever more complex throughout the years so properly modeling this portion of the process has the potential to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we will show results of a new approach that incorporates mask process modeling. We will also show results of testing a new dynamic mask bias application used during OPC verification.

Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers. This patterning is even more challenging for advanced technologies such as the 45nm node where most of the process optimization is done for minimum pitch dense lines. Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features (SRAF) to assist the patterning of isolated trenches structures. Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: - Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation - Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with silicon process window analysis - Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement characterization of specific test patterns - Maskshop manufacturability through CD measurements and inspection capability Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF for trenches.

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17mm2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

The use of sub-resolution assist features (SRAFs) is a necessary and effective technique to mitigate the proximity effects resulting from low-k1 imaging with aggressive illumination schemes. This paper investigates the application of one implementation of Inverse Lithography Technology (ILT) to determine optimized SRAF placement and size. In contrast to traditional rule-based methods in which SRAF placement and size are typically predetermined and frozen in place, unmodified during OPC, ILT allows for the simultaneous placement and sizing of SRAFs during target inversion to maximize image quality while also maintaining margin against sidelobe printing. Furthermore, ILT enables SRAF placement for random as well as periodic patterns. In this paper, SRAF placement using this approach is studied through simulations. The computed mask and simulation results are shown to illustrate effectiveness of ILT-generated SRAF features.