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In this paper, a standard CMOS technology is used to fabricate high performance Si/Si0.68Ge0.32 pMOS devices with thin Si cap layers. Careful fine-tuning of the epitaxial growth conditions and pre-epi surface treatment leads to the deposition of high quality facet free epitaxial layers.As compared to Si-only devices, the Si/Si0.68Ge0.32 devices exhibit strongly enhanced mobilities. For the best devices an increase by a factor of 2.5 can be seen. This enhanced mobility behaviour results in a strong increase of the on-state current and transconductance for devices with a gate length down to 0.13 μm. [Copyright &y& Elsevier]

Abstract: In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO2 than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25nm. The possible reasons for the observed effect are discussed. [Copyright &y& Elsevier]

Abstract: Inherently smaller cross-sectional area of heavily doped source/drain regions (HDDs) in multiple gate transistors is known to give rise to a higher contact resistance between Si and HDD silicide as compared to a planar transistor with similar width of the Si channel. In order to characterize the contact resistance, multiple gate FETs have been fabricated with fin widths and gate lengths down to 18 and 45nm, respectively. Experiments performed by varying layout and technology parameters show that Nickel silicide forms wrapped contacts around HDDs. Further, the silicidation process is shown to be fully siliciding HDDs in devices with narrow fins, where a selective epitaxial growth of Si has been performed in HDDs. [Copyright &y& Elsevier]

The transfer characteristic at room temperature of FinFETs processed for sub-10 nm technologies could always be explained by solving Poisson equation throughout the channel – dielectric interface. Various methods for the MOSFET parameters estimation are proposed in the literature. In this paper, the electrical parameters extraction technique based on the Y-function methodology is reminded. Low frequency noise is presented considering three major noise sources: 1/ f noise associated to carrier trapping-detrapping in the gate oxide, channel carrier mobility fluctuations and generation-recombination noise related to traps located in the depletion zone of the device. Theory and methodology in order to identify the 1/ f noise mechanism and to have information of the process induced traps in the silicon film using the noise spectroscopy technique are revisited. [ABSTRACT FROM AUTHOR]

Low frequency noise measurements are used as a non-destructive diagnostic tool in order to evaluate the quality of the gate oxide and the silicon film of sub-10 nm triple-gate Silicon-on-Insulator (SOI) FinFETs. It was found that the carrier number fluctuations explain the 1/ f noise in moderate inversion for n- and p-FinFETs, which allows estimating the gate oxide trap densities. The noise spectroscopy with respect to temperature (study of the generation-recombination noise) led to the identification of the traps located in the transistors silicon film. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO2 gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias (V BG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance (g mf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages (V FG) around 0.8V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in g mf is also found in TiN/HfO2 devices for V FG around 1.1V. Under the accumulation V BG conditions in which FBEs are observed, front gate switch drain current (I D) transients are also appreciated. Interestingly, a change in the shape of I D transients is observed for V FG conditions in which EVB majority carriers are injected into the floating fin. The I D transients, as well as the second peak of g mf and other FBEs, are found to gradually diminish for strong accumulation V BG conditions or reduced geometry dimensions. [Copyright &y& Elsevier]

Abstract: This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110nm long channel achieve an intrinsic gain of 25dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body. [Copyright &y& Elsevier]

Abstract: High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate FETs with narrow fins. Reduction of specific contact resistance by selective epitaxial growth of Si in heavily doped S/D regions of a multiple gate FET helps with achieving low S/D resistance. This paper addresses integration of low temperature selective epitaxial growth process into multiple gate FET processing. Our experimental results show more than 30% reduction in the parasitic S/D resistance for 16-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate NFETs with less than 20-nm wide fins. A follow up of this work with HfO2-TiN gate stack shows more than 20% improvement in the drive current at a constant I OFF for 40-nm selective epitaxial growth of Si in the heavily doped S/D regions of multiple gate FETs. [Copyright &y& Elsevier]