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Detailed analysis of device behaviour on the zero-temperature coefficient (ZTC) points for microwave GaAs based high-electron mobility transistor is presented by means of on-wafer measurements over the temperatures between −40 and 150 °C. This zero temperature coefficient points found not only in the transfer and transconductance curve but also in intrinsic transconductance g mo , output conductance g ds , small signal gain S 21 , and minimum noise figure NF min also exhibits ZTC. It is found that the zero temperature coefficients points are impacted by both threshold voltage and drain bias. The transfer current base, ZTCI ds moved from 0.1 V to −0.2 V of V gs trace and transconductance based, ZTCg m moved from −0.3 V to −0.6 V of V gs trace with the drain bias, V ds varies from 1 V to 5 V. The behaviour of some intrinsic equivalent circuit parameters along with cut-off frequency, f t at both ZTC bias points opens some crucial insight and opportunities in microwave device design for low and high temperature applications.

Linear and nonlinear characteristics of a 0.5 μm × (2 × 100) μm gate double heterojunction AlGaAs/InGaAs/GaAs pseudomorphic high-electron mobility transistor have been investigated using a two-tone intermodulation distortion (IMD) measurement technique. The results indicate a significant modification on the IMD output power components such as fundamental, IMD2, IMD3, IMD4, IMD5 and IMD7 with the variation of biasing conditions, input power, frequency and temperature. Increase in input power affects the output current as well as the parasitic resistances and subsequently the threshold voltage reduces, resulting to an increase in the output IMD power. On the other hand, increase in frequency & temperature reduces the magnitude of the output IMDs. The temperature affects the output current as well as the parasitic resistances and the threshold voltage, results a decrease in the output IMD power. The threshold voltage shifts negatively with temperature and modifies the notch/null’s position of the second and higher order IMD output power components. This investigation is valuable for the circuit designers to evaluate the best biasing option in terms of minimum distortion, maximum gain for future design optimizations.

This study focuses on 3-D multilayer monolithic integration of vertical-oriented double-heterojunction AlGaAs/InGaAs/GaAs based pseudomorphic high electron mobility transistors. The effects of the presence of 3-D components above the active layer were accomplished by comparing three multilayer fabricated device of different thickness with a virgin device where the thickness of the 3-D components e.g., both metal and polyimide layer were varied. The output current, on-state gate leakage, transconductance are found to be decrease with the increase in thickness of the 3-D components and on the other hand, the on-state resistance, knee voltage and off-state gate leakage is increased. Lastly, the thermal influences on the device behaviour such as off-state and on-state gate leakage, barrier inhomogeneities at Schottky contacts, zero temperature coefficients at the transfer curve, and the threshold voltage as a function of drain bias were measured and analyzed for the both pre and post fabricated multilayer devices. These effective comparisons in terms of thickness and temperature of the both device are useful for future designs and optimizations of multilayer vertical stacked 3-D MMICs.

Multibias and thermal characterizations on 0.25 μm × (2 × 100) μm AlGaN/GaN/SiC HEMT and 0.5 μm × (2 × 100) μm AlGaAs/InGaAs pseudomorphic HEMT have carried out for the first time. Two competitive device technologies are investigated with the variations of bias and temperature in order to afford a detailed realization of their potentialities. The main finding includes the self heating effect in the GaN device, zero temperature coefficient points at the drain current and transconductance in the GaAs device. The thermal resistance RTH of 7.1, 8.2 and 9.4 °C mm/W for the GaN device was estimated at 25, 75 and 150 °C respectively which are consistent with those found in the open literature. The temperature trend of the threshold voltage VT, Schottky barrier height ϕb, sheet charge densities of two dimensional electron gas ns, and capacitance under the gate Cg are exactly opposite in the two devices; whereas the knee voltage Vk, on resistance Ron, and series resistance Rseries are shows similar trend. The multi-bias and thermal behavior of the output current Ids, output conductance gds, transconductance gm, cut-off frequency ft, maximum frequency fmax, effective velocity of electron, veff and field dependent mobility, μ demonstrates a great potential of GaN device. These results provide some valuable insights for technology of preference for future and current applications.

Thermal and small-signal model parameters analysis have been carried out on 0.5 μm × (2 × 100 μm) AlGaAs/GaAs HEMT grown on semi-insulating GaAs substrate and 0.25 μm × (2 × 100 μm) AlGaN/GaN HEMT grown on SiC substrate. Two different technologies are investigated in order to establish a detailed understanding of their capabilities in terms of frequency and temperature using on-wafer S-parameter measurement over the temperature range from −40 to 150 °C up to 50 GHz. The equivalent circuit parameters as well as their temperature-dependent behavior of the two technologies were analyzed and discussed for the first time. The principle elevation or degradation of transistor parameters with temperature demonstrates the great potential of GaN device for high frequency and high temperature applications. The result provides some valuable insights for future design optimizations of advanced GaN and a comparison of this with the GaAs technology.

Investigation of the third-order intercept point, IP3 and nonlinear distortion level, NDL for pre-and post-multilayer processed GaAs pHEMTs has been accomplished by employing two-tone intermodulation distortion measurements. The third-order intercept point is a biasing, input power, frequency-dependent term, particularly related to the fundamental and third-order intermodulation distortion component and the study extended from low to high temperatures. The main findings are that the output referenced OIP3 decreased while the input referenced IIP3 increased with frequency at peak transconductance condition and the study further extended to multi-bias operation condition. Within the measured temperature range, the IP3 and NDL modified significantly following the behaviour of IMD3 distortion. This investigation of IP3 is utilized to measure how much distortion is created and referring this to the antenna input gives a straightforward strategy to decide whether or not the spec can be met. On the other hand, analysis of NDL is vital for choosing the most excellent biasing alternative with the entryway measurements of the device to create a compromise agreeing to the desired utilization.

This study deals with the uniformity investigation and comparison on the typical behaviour of pseudomorphic high electron mobility transistors (pHEMTs) before and after the 3-D multilayer fabrication. There are seven multilayer fabricated pHEMTs compared with the seven virgin pHEMTs based on drain-source input current, output current, transconductance, off state leakage behaviour, threshold voltage, knee voltage, on-resistance, Schottky barrier height, ideality factor, reverse saturation current, small signal gain and current gain. Below 10% changes in performance can be seen after multilayer fabrication compare to virgin samples and apart from these exceptions, the discrepancies are well within the tolerance and less than 3% in terms of Schottky behaviour. We show that, the application of the 3D-MMIC technology does not cause any visible destruction of pHEMTs performance using seven different samples before and after the multilayer fabrication.

Large parasitic series resistances of the heterostructure bipolar transistors are shown to cause a sharp rise in the base current of the Gummel plot at high current levels. This effect is analysed and attributed to a forward-biased base–collector junction due to the large voltage drop across the collector series resistance of the device. The occurrence of this effect results in a severe reduction in current gain of the device at high current levels. A DC Ebers–Moll model is presented with all the parameters extracted from DC characterisation of the HBT, and an excellent fit between the model and experimental data is obtained. The method can be used to determine the base, collector and emitter series resistances of the bipolar transistors for DC applications. Finally, the effect of temperature on the onset of this effect is demonstrated.