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This paper presents a 3-D statistical simulation study of Multi-fin junction FinFET for different technology nodes 32 nm, 24 nm & 10 nm. For each and every technology node their corresponding Electrical parameters like on current (Ion), off current (Ioff), threshold voltage (Vth) are reported in the paper and also RF/Analog parameters like transconductance (gm), output conductance (gd), intrinsic gain (gm/gd) are reported. And also parameters like Electric field (E), Electron density (ne), Electron mobility (μ) which are measured across the device length are simulated. The proposed structure showed performance improvement in all the parameters when the technology node is decreased.

In this paper, we design, simulate and analyze FinFET with different materials, corresponding variation in ID VS VGS, transconductance, subthreshold slope. There is an increase in ON current on using a high-k dielectric material and subsequently an improvement in other parameters like subthreshold slope and transconductance.