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We present a Montecarlo simulator developed in Matlab ® for the analysis of a Single Photon Avalanche Diode (SPAD)-based Complementary Metal-Oxide Semiconductor (CMOS) flash Light Detection and Ranging (LIDAR) system. The simulation environment has been developed to accurately model the components of a flash LIDAR system, such as illumination source, optics, and the architecture of the designated SPAD-based CMOS image sensor. Together with the modeling of the background noise and target topology, all of the fundamental factors that are involved in a typical LIDAR acquisition system have been included in order to predict the achievable system performance and verified with an existing sensor.

This paper presents the design, implementation and characterization results of a pixel-level readout chain integrated with a FET-based terahertz (THz) detector for imaging applications. The readout chain is fabricated in a standard 150-nm CMOS technology and contains a cascade of a preamplification and noise reduction stage based on a parametric chopper amplifier and a direct analog-to-digital conversion by means of an incremental ΣΔ converter, performing a lock-in operation with modulated sources. The FET detector is integrated with an on-chip antenna operating in the frequency range of 325⁻375 GHz and compliant with all process design rules. The cascade of the FET THz detector and readout chain is evaluated in terms of responsivity and Noise Equivalent Power (NEP) measurements. The measured readout input-referred noise of 1.6 μ V r m s allows preserving the FET detector sensitivity by achieving a minimum NEP of 376 pW/ Hz in the optimum bias condition, while directly providing a digital output. The integrated readout chain features 65-dB peak-SNR and 80-μ W power consumption from a 1.8-V supply. The area of the antenna-coupled FET detector and the readout chain fits a pixel pitch of 455 μm, which is suitable for pixel array implementation. The proposed THz pixel has been successfully applied for imaging of concealed objects in a paper envelope under continuous-wave illumination.

This paper reviews the state of the art of single-photon avalanche diode (SPAD) image sensors for time-resolved imaging. The focus of the paper is on pixel architectures featuring small pixel size (<25 μm) and high fill factor (>20%) as a key enabling technology for the successful implementation of high spatial resolution SPAD-based image sensors. A summary of the main CMOS SPAD implementations, their characteristics and integration challenges, is provided from the perspective of targeting large pixel arrays, where one of the key drivers is the spatial uniformity. The main analog techniques aimed at time-gated photon counting and photon timestamping suitable for compact and low-power pixels are critically discussed. The main features of these solutions are the adoption of analog counting techniques and time-to-analog conversion, in NMOS-only pixels. Reliable quantum-limited single-photon counting, self-referenced analog-to-digital conversion, time gating down to 0.75 ns and timestamping with 368 ps jitter are achieved.