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Due to their low production costs, small weight, printability, solution processing, and the possibility of using flexible substrates, organic solar cells (OSCs) exhibit strong potential to be used in future solar cell technology. Major specifications for the commercialization of OSCs are the long life span of OSC devices, enhanced environmental stability and a sufficiently high power conversion efficiency (PCE). The development of low energy gap organic polymers, transport materials and multi-layer system architecture has been effective in achieving higher PCE. However, overcoming environmental stability and sustaining a longer life span are a major challenge. The instability of OSCs is the dynamic mechanism, mostly induced due to the combined impact of oxygen, incident light, and ambient, as well as processing, temperature. Studies have reported that thermal annealing of the active layer tends to a shift in the phase morphology, which typically occurs either because of the vertical phase separation or because of the process of donor–acceptor phase segregation. In this paper, various factors that affect the performance of the OSC have been comprehensively studied. Factors such as thermal stress, vertical phase segregation, material composition and tradeoff between thickness and light absorption have been discussed. This paper mainly reviews the measures carried out to improve the efficiency of conventional polymer-fullerene-based bulk-heterojunction OSCs and reports the different techniques to address these issues. [ABSTRACT FROM AUTHOR]

In this paper, asymmetric drain (ASD) underlap channel dopant-segregated Schottky barrier (DSSB) silicon-on-insulator (SOI) MOSFET has been proposed to improve the scalability and high-frequency performance of DSSB SOI MOSFET. The asymmetry of this device lies in the spacer thickness at the drain which creates an underlap channel with the same dopant-segregation length as that of the overlap channel at the source. The presence of overlap at the source and underlap at the drain of this device not only makes it immune to short-channel effects and the gate-induced drain leakage but also improves the analog figures of merit such as transconductance, intrinsic gain and unity-gain frequency of the device. In addition to this, the inverter power dissipation and the ring-oscillator delay in an optimized ASD underlap device are reduced by ~40% and ~20%, respectively, over the symmetric source/drain overlap and underlap channel devices. Thus, the significant improvement in both digital and analog figures of merit at nanoscale shows the suitability of the proposed device for low-power mixed-signal circuits. The proposed fabrication flow of this novel device is also similar to the DSSB SOI MOSFET flow and demonstrates the use of conventional CMOS processes. [ABSTRACT FROM AUTHOR]