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A new, 600V, RESURF LDMOS structure promising improvement on reliability, low on-resistance, and wide SOA region was proposed. The proposed LDMOS structure can reduce the electric field at silicon surface by about 40% using p-bottom layer for charge compensation without p-top layer. As carrier trapping into oxide at high electric field can be restrained, high reliability characteristics are expected. Most current flows around the silicon surface when the LDMOS turns on. However, in the proposed LDMOS, impact ionisation is repressed and current driving ability is increased by about 24%, voltage range is widened by 6% in SOA region because it has the low surface electric field. R/sub on,sp/ was improved by 15% when compared to the conventional LDMOS at the same breakdown voltage rating because there is no blocking layer in the drift region. This proposed LDMOS can also save one mask layer more than the conventional one.

In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free NPN transistor and PNP transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for NPN and PNP transistor are 10 GHz and 9 GHz, the values of BVceo for the NPN and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.