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Abstract: We developed a fabrication process for planarized multi-layer Nb SFQ circuits. This new process has several new steps for achieving a planarized multi-layer structure with a high critical current density. We have so far fabricated about 30 wafers, and we have measured the characteristics of Josephson junctions in multi-layer structures. We confirmed small spreads and high reproducibility in the critical current, and we also achieved a high junction yield. In contrast, we detected a minor degradation of the gap voltage, which had no serious influence on circuit operation. Based on the measured results, we believe that planarization was the most probable cause for this degradation. [Copyright &y& Elsevier]

Abstract: We developed a 10 kA/cm2 Nb fabrication process, whose device structure was composed of six planarized Nb-layers, an Nb/AlO x /Nb junction layer, an Mo resistor layer, and SiO2 insulator layers to make larger scale, higher speed single-flux-quantum (SFQ) circuits that have more than 100 k junctions.It is very important to evaluate the process reliability in relation to the uniformity of the device parameters and the defect rate of the fabrication process. To evaluate the process reliability, we designed and tested many kinds of process test circuits, including 100 k junctions and 60-k serially connected contacts. We obtained excellent insulation properties, even in the six-Nb-layer structure. The standard deviations of the critical currents for 2000 1.2-μm-square junctions were less than 1.9%. We obtained a critical current of more than 8 mA, even for the 60-k serially connected contacts. Based on these results, we obtained sufficient reliability to realize the SFQ circuits including more than 100 k junctions. [Copyright &y& Elsevier]

Mechanical polishing (MP) is a key technology for fabricating multi-layer, large-scale integrated Nb SFQ circuits. This process, however, could possibly influence junction characteristics. We studied the impact of a planarization process based on MP on the junction characteristics. The process, performed either before or after junction fabrication, did not significantly degrade the junction characteristics. We successfully demonstrated multi-layer integrated circuits with six Nb layers planarized by MP. [Copyright &y& Elsevier]

We have been developing a 10-kA/cm2 advanced Nb process in order to fabricate larger scale and higher speed SFQ circuits with over 100k junctions. We have proposed a planarized multi-layer structure, which consists of a Nb/AlOx/Nb junction layer, 4 Nb wiring layers, a Nb layer for DC power, a Nb ground plane, SiO2 insulator layers, and a Mo resistor layer. Process technologies for fabricating 1.0-μm2 junctions with high JC of 10 kA/cm2 and 1σ of 1.4% and Mo resistors with R⧠ of 2.4 Ω have been developed. A new planarization technology called caldera, which is applicable to patterns of various sizes, has been developed. This process consists of reactive ion etching (RIE) with a reverse mask, bias sputtering, and mechanical polishing planarization (MPP). We have now successfully developed all the component technologies required for the advanced Nb process. We have implemented these technologies for the through process and fabricated a structure with six planarized Nb layers, including Nb/AlOx/Nb junctions, Mo resistors, and contacts. In this structure, we obtained excellent current–voltage characteristics for the junctions, sufficient superconducting characteristics for the contacts, and good insulation characteristics between the wiring layers. [Copyright &y& Elsevier]

Abstract: We investigated the most suitable device structure for large-scale SFQ circuits and propose a new Nb 10-layer device structure that is composed of active layers including junctions at the top, PTL layers in the middle and DC power layers at the bottom. This device structure enables us to reduce the influence of the magnetic field due to large bias currents and to form a Nb/AlO x /Nb junction layer in the last part of the fabrication sequence. To achieve this structure, we developed a higher quality planarization that could remove the residual slight roughness after standard caldera planarization. We fabricated a diagnostic chip that is composed of test elements such as junctions, contacts, resistors and many kinds of process test patterns. We obtained sufficient characteristics for the diagnostic chips. Moreover, to evaluate the fabrication process, we designed and fabricated several shift registers. We confirmed the correct operation of an up to 2560-bit shift register having 10,281 junctions. [Copyright &y& Elsevier]

Abstract: We have evaluated the inductances of the striplines and the stacked vias which are realized in the planarized 6-Nb-layer device fabricated by our advanced Nb fabrication process. The inductances of centered and off-center striplines were compared with inductances of the microstrip lines which had insulators with the same thicknesses as an insulator or a thinner insulator between the signal line and the ground plane in the stripline. The centered striplines showed the sheet inductances about 0.65 times as much as those of the microstrip lines. The factor would be useful for designing passive transmission lines (PTLs) based on the stripline, and would provide the estimate of the line width of the PTLs. The stacked vias showed a small increase of ∼0.1 pH in inductance every additional a via stacked on top of a via. A comparison between the inductance of the stacked via and that of conventional vias revealed that the stacked vias are effective in reduction of layout areas and parasitic inductances. [Copyright &y& Elsevier]

We fabricated Nb/AlOx/Nb junctions using electron cyclotron resonance (ECR) plasma etching. When junctions were fabricated using ECR plasma etching for the junction definition process, they exhibited leaky current–voltage (I–V) characteristics and poor critical current (Ic) uniformity. This indicated that ECR plasma etching damaged the junction barrier. Excellent junction characteristics, on the other hand, were obtained by anodizing the junction periphery at 15 V after ECR plasma etching. This meant that the damaged region was within 14 nm from the junction periphery and that the leakage paths in the damaged region induced by ECR plasma were completely passivated by anodization. The uniformity of Ic in junctions fabricated using ECR plasma etching and anodization was quite good. The standard deviation, 1σ, in Ic was estimated to be 1.4% for a series array of 1000, 0.93-μm2 junctions with a critical current density of 9.8 kA/cm2. [Copyright &y& Elsevier]