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Photonic integrated circuits (PIC) devices are impacted by fabrication tolerances and therefore, prior knowledge of such variations could improve the PIC fabrication process and overall yield. This paper presents a method for predicting the fabrication impacts on a telecommunication optical digital to analog converter (oDAC)-based pulse amplitude modulator level four (PAM-4) transmitter as a case study where the certainty of this passive device is subjected to random variation. Our findings allow us to estimate the production yield in a fabrication scenario using the symbol error rate (SER) benchmark and this contributes to the study of the viability of oDAC PAM-4 transmitters to replace conventional electrical digital to analog converter (eDAC) PAM-4 transmitters. [ABSTRACT FROM AUTHOR]

We analyze the two classic methods for chirped Integrated Bragg Gratings (IBGs) in Silicon-on-Insulator technology using the transfer matrix method based on the effective refractive index (neff) technique, which translates the geometry of an IBG into a matrix of neff depending on the wavelength. We also implement a procedure that allows engineering of the chirped IBG parameters, given a required bandwidth (BW) and group delay (GD). Finally, a complementary method for designing chirped IBG is proposed, showing a significant improvement in the bandwidth of the device or a moderation in the variation of the geometrical parameters of the grating. [ABSTRACT FROM AUTHOR]

Photonic neural network chips have been widely studied because of their low power consumption, high speed and large bandwidth. Using amplitude and phase to encode, photonic chips can accelerate complex-valued neural network computations. In this article, a photonic complex-valued neural network (PCNN) chip is designed. The scale of the single-core PCNN chip is limited because of optical losses, and the multicore architecture of the chip is used to improve computing capability. Further, for improving the performance of the PCNN, we propose the transformation layer, which can be implemented by the designed photonic chip to transform real-valued encoding to complex-valued encoding, which has richer information. Compared with real-valued input, the transformation layer can effectively improve the classification accuracy from 93.14% to 97.51% of a 64-dimensional input on the MNIST test set. Finally, we analyze the multicore computation of the PCNN. Compared with the single-core architecture, the multicore architecture can improve the classification accuracy by implementing larger neural networks and has better phase noise robustness. The proposed architecture and algorithms are beneficial to promote the accelerated computing of photonic chips for complex-valued neural networks and are promising for use in many applications, such as image recognition and signal processing. [ABSTRACT FROM AUTHOR]