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The spatial light modulators (SLMs) at the Fourier planes of a conventional joint-transform correlation (JTC) are eliminated using simple grating filters such as rectangular and triangular ones. To achieve this goal, two non-conventional real-time JTC architectures are proposed: (a) the grating filter is used along with a heterodyning and one-dimensional optical scanning technique to capture the cross-correlation functions of the input images without major processing and (b) the one-dimensional optical scanning is eliminated to achieve a faster (but a little bit more complicated) processing. The proposed techniques significantly reduce the time processing needed for real-time applications by eliminating the drawbacks of the non-ideal characteristics of the SLMs.

Optical shadow-casting (OSC) technique has shown excellent potential for optically implementing two-operand parallel logic gates and array logic operations. The 16 logic functions for two binary patterns (variables) are optically realizable in parallel by properly configuring an array of 2×2 light emitting diodes. In this paper, we propose an enhanced OSC technique for implementing four-operand parallel logic gates. The proposed system is capable of performing 216 logic functions by simply programming the switching mode of an array of 4×4 light emitting diodes in the input plane. This leads to an efficient and compact realization scheme when compared to the conventional two-operand OSC system.

The pattern matching for fingerprints requires a large amount of data and computation time. Practical fingerprint identification systems require minimal errors and ultrafast processing time to perform real-time verification and identification. By utilizing the two-dimensional processing capability, ultrafast processing speed and non-interfering communication of optical processing techniques, fingerprint identification systems can be implemented in real-time. Among the various pattern matching systems, the joint transform correlator (JTC) has been found to be inherently suitable for real-time matching applications. Among the various JTCs, the fringe-adjusted JTC has been found to yield significantly better correlation output compared to alternate JTCs. In this paper, a fingerprint identification system has been developed based on the fringe-adjusted JTC. Since all pattern matching systems suffer from high sensitivity to distortions, the synthetic discriminant function concept has been incorporated in fringe-adjusted JTC to ensure distortion-invariant fingerprint identification.

A new design approach for a three-step modified signed-digit (MSD) adder is presented that can be optically implemented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position encoding scheme. The proposed design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The optical binary logic gates are obtained by simply programming the decoding masks of a shadow-casting-based optical logic gate system. The proposed scheme results in a simple, compact, and efficient optical binary gate-based parallel addition system.

A new synthetic discriminant-function-based amplitude modulated phase-only filtering technique is proposed for scale invariant pattern recognition. This technique has been found to yield improved correlation output when compared with the alternate techniques. The proposed technique is inherently suitable for optical implementation using the currently available spatial light modulators. Simulation results confirm the effectiveness of the proposed technique.

The trinary signed-digit (TSD) number system is of interest for ultrafast optoelectronic computing systems since it permits parallel carry-free addition and borrow-free subtraction of two arbitrary length numbers in constant time. In this paper, a simple coding scheme is proposed to encode the decimal number directly into the TSD form. The coding scheme enables one to perform parallel one-step TSD arithmetic operation. The proposed coding scheme uses only a 5-combination coding table instead of the 625-combination table reported recently for recoded TSD arithmetic technique.

A variety of algorithms for computing complex elementary functions based on the quaternary signed-digit (QSD) number system are proposed. An arithmetic unit that performs parallel one-step addition (subtraction), multiplication, and division is proposed to perform the computations of elementary functions such as square root, logarithmic, exponential, and other related functions. An optoelectronic-correlator-based architecture is suggested for implementing the proposed QSD elementary function algorithms. We used the symbolic substitution technique to reduce the number of the computation rules involved.

A single-step optoelectronics symbolic substitution scheme to handle parallel modified signed-digit (MSD) arithmetic operations is proposed. Conversion algorithms from MSD numbers into a canonical MSD representation are provided. The canonical MSD numbers have the property that no two consecutive digits are non-zero. The addition operation of two CMSD numbers is performed in one step. It will be shown that through the use of CMSD representation, the number of symbolic substitution rules in an optical content-addressable memory (CAM) based system is significantly reduced. The number of symbolic substitution rules can be further reduced to an optimum value through a proposed shared content-addressable memory optical set-up. Further, the proposed optical scheme doubles the storage efficiency of the shared content-addressable memory.

The effect of varying the input scene illumination and noise on the performance of binary and fringe-adjusted joint transform correlators (JTCs) has been investigated in this paper. Simulation results show that the fringe-adjusted JTC yields superior correlation output when compared with the binary JTC for all types of input scenes affected by both illumination and noise. Furthermore, the binary JTC has been found to yield a good correlation output when zero mean, unity variance Gaussian white noise is added to input scenes affected by poor illumination.

An efficient technique for the design of multiple-valued logic circuits using polarization-encoded optical shadow-casting is presented. As an illustration, a trinary full subtracter is designed using this technique. The resulting logic unit is compared with those obtained by using other algorithms.

The correlation discrimination between the target and the reference in a joint transform correlator (JTC) deteriorates rapidly with an increase in the number of non-target objects in the input scene. The correlation peak in a JTC is increased significantly by updating the input plane information based on the correlation plane information. Simulation results are presented to verify the effectiveness of the proposed feedback scheme.