Search

The greatest challenge for 65-nm contact holes and via printing is ensuring an acceptable process window (250-nm DoF @ 8% EL) for a wide range of pitches with a MEEF lower than 3.5. To print dense contact holes / vias with a CD less than 100-nm, very high Numerical Apertures (≥ 0.85) are required. Consequently DoF through pitch is dramatically reduced, such that it becomes absolutely necessary to develop new techniques to enhance process latitude. In this paper, we will study the use of customized illuminations formed by combination of small radius conventional illumination and quasar. Generically, this type of illumination is commonly referred to as 5-pole illumination. Specifically this paper, the “windmill” and “soft quasar” options are investigated. These designs are based upon the assumption, that there is a way to optimize for all pitches, the imaging lens pupil filling with diffracted orders. Using a combination of aerial image simulations and experimental (double) exposures, the optimal 5-pole illumination designs are derived, with their simulated performance being compared to conventional illumination settings. For the optimised designs, experimental data is presented for “real” device structures based on the Crolles2 65-nm technology design rules.

In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor [1], improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented. In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.

The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.