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Semiconductor nanowires (NWs) in horizontal configuration could provide a path for scalable NW-based devices. Bottom–up large-scale manufacturing of these nanostructures by selective area epitaxy (SAE) relies on precise nanopatterning of various shapes on the growth masks. Electron beam lithography offers an extraordinary accuracy suited for the purpose. However, this technique is not economically viable for large production as it has a low throughput and requires high investment and operational costs. Nanoimprint lithography (NIL) has the potential to reduce fabrication time and costs significantly while requiring less sophisticated equipment. In this work, we utilize both thermal and UV NIL for patterning substrates for SAE, elucidating the advantages and disadvantages of each lithography technique. We demonstrate the epitaxial growth of Ge and GaAs NWs on these substrates, where we observe high-quality mono-crystalline structures. Even though both processes can produce small uniform structures suitable for SAE, our results show that UV NIL proves to be superior and enables reliable and efficient patterning of sub-100 nm mask features at the wafer scale. [ABSTRACT FROM AUTHOR]

Selective area epitaxy (SAE) provides the path for scalable fabrication of semiconductor nanostructures in a device-compatible configuration. In the current paradigm, SAE is understood as localized epitaxy, and is modelled by combining planar and self-assembled nanowire growth mechanisms. Here we use GaAs SAE as a model system to provide a different perspective. First, we provide evidence of the significant impact of the annealing stage in the calculation of the growth rates. Then, by elucidating the effect of geometrical constraints on the growth of the semiconductor crystal, we demonstrate the role of adatom desorption and resorption beyond the direct-impingement and diffusion-limited regime. Our theoretical model explains the effect of these constraints on the growth, and in particular why the SAE growth rate is highly sensitive to the pattern geometry. Finally, the disagreement of the model at the largest pitch points to non-negligible multiple adatom recycling between patterned features. Overall, our findings point out the importance of considering adatom diffusion, adsorption and desorption dynamics in designing the SAE pattern to create pre-determined nanoscale structures across a wafer. These results are fundamental for the SAE process to become viable in the semiconductor industry. [ABSTRACT FROM AUTHOR]

Semiconductor nanowires (NWs) are believed to play a crucial role for future applications in electronics, spintronics and quantum technologies. A potential candidate is HgTe but its sensitivity to nanofabrication processes restrain its development. A way to circumvent this obstacle is the selective area growth technique. Here, in-plane HgTe nanostructures are grown thanks to selective area molecular beam epitaxy on a semi-insulating CdTe substrate covered with a patterned SiO 2 mask. The shape of these nanostructures is defined by the in-plane orientation of the mask aperture along the <110>, <11¯0>, or <100> direction, the deposited thickness, and the growth temperature (GT). Several micron long in-plane NWs can be achieved as well as more complex nanostructures such as networks, diamond structures or rings. A good selectivity is achieved with very little parasitic growth on the mask even for a GT as low as 140 °C and growth rate up to 0.5 monolayer per second. For <110> oriented NWs, the center of the nanostructure exhibits a trapezoidal shape with {111}B facets and two grains on the sides, while <11¯0> oriented NWs show {111}A facets with adatoms accumulation on the sides of the top surface. Transmission electron microscopy observations reveal a continuous epitaxial relation between the CdTe substrate and the HgTe NW. Measurements of the resistance with four-point scanning tunneling microscopy indicates a good electrical homogeneity along the main NW axis and a thermally activated transport. This growth method paves the way toward the fabrication of complex HgTe-based nanostructures for electronic transport measurements., (© 2024 IOP Publishing Ltd. All rights, including for text and data mining, AI training, and similar technologies, are reserved.)

Increasing quantum confinement in semiconductor quantum dot (QD) systems is essential to perform robust simulations of many-body physics. By combining molecular beam epitaxy and lithographic techniques, we developed an approach consisting of a twofold selective area growth to build QD chains. Starting from 15 nm-thick and 65 nm-wide in-plane In 0.53 Ga 0.47 As nanowires on InP substrates, linear arrays of In 0.53 Ga 0.47 As QDs were grown on top, with tunable lengths and separations. Kelvin probe force microscopy performed at room temperature revealed a change of quantum confinement in chains with decreasing QD sizes, which was further emphasized by the spectral shift of quantum levels resolved in the conduction band with low temperature scanning tunneling spectroscopy. This approach, which allows the controlled formation of 25 nm-thick QDs with a minimum length and separation of 30 nm and 22 nm respectively, is suitable for the construction of scalable fermionic quantum lattices., (© 2024 IOP Publishing Ltd.)

In-plane InAs nanowires and nanowire networks show great potential to be used as building blocks for electronic, optoelectronic and topological quantum devices, and all these applications are keen to grow the InAs materials directly on Si substrates since it may enable nanowire electronic and quantum devices with seamless integration with Si platform. However, almost all the in-plane InAs nanowires and nanowire networks have been realized on substrates of III-V semiconductors. Here, we demonstrate the selective area epitaxial growth of in-plane InAs nanowires and nanowire networks on Si substrates. We find that the selectivity of InAs growth on Si substrates is mainly dependent on the growth temperature, while the morphology of InAs nanowires is closely related to the V/III flux ratio. We examine the cross-sectional shapes and facets of the InAs nanowires grown along the 〈110〉, 〈100〉 and 〈112〉 orientations. Thanks to the non-polar characteristics of Si substrates, the InAs nanowires and nanowire networks exhibit superior symmetry compared to that grown on III-V substrates. The InAs nanowires and nanowire networks are zinc-blende (ZB) crystals, but there are many defects in the nanowires, such as stacking faults, twins and grain boundaries. The crystal quality of InAs nanowires and nanowire networks can be improved by increasing the growth temperature within the growth temperature window. Our work demonstrates the feasibility of selective area epitaxial growth of in-plane InAs nanowires and nanowire networks on Si substrates., (© 2023 IOP Publishing Ltd.)

Selective area growth of In(Ga)N/GaN nanocolumns was performed on GaN-buffered Si(111) substrates by plasma-assisted molecular beam epitaxy. Undoped and Si-doped GaN buffer layers were first grown on Si(111) substrates, showing photoluminescence excitonic emission without traces of other low energy contributions, in particular, the yellow band. The GaN buffer surface roughness (between 10 and 14 nm, the rms value in a 10 × 10 μm2 area) was low enough to allow the fabrication of a thin (7 nm thick) well defined Ti nanohole mask, for the selective area growth. Ordered In(Ga)N/GaN nanocolumns emitting from the ultraviolet (3.2 eV) to the infrared (0.78 eV) were obtained. The morphology and the emission efficiency of the In(Ga)N/GaN nanocolumns emitting at a given wavelength could be substantially improved by tuning the In/Ga and total III/N ratios. An estimated internal quantum efficiency of 36% was derived from photoluminescence data for green emitting nanocolumns. [ABSTRACT FROM AUTHOR]

Semiconductor p-n junctions are essential building blocks of electronic and optoelectronic devices. Although vertical p-n junction structures can be formed readily by growing in sequence, lateral p-n junctions normal to surface direction can only be formed on specially patterned substrates or by post-growth implantation of one type of dopant while protecting the oppositely doped side. In this study, we report the monolithic formation of lateral p-n junctions in GaAs nanowires (NWs) on a planar substrate sequentially through the Au-assisted vapor-liquid-solid selective lateral epitaxy using metalorganic chemical vapor deposition. p-type and n-type segments are formed by modulating the gas phase flow of p-type (diethylzinc) and n-type (disilane) precursors in situ during nanowire growth, allowing independent sequential control of p- and n-doping levels self-aligned in-plane in a single growth run. The p-n junctions formed are electrically characterized by fabricating arrays of p-n junction NW diodes with coplanar ohmic metal contacts and two-terminal I - V measurements. The lateral p-n diode exhibits a 2.15 ideality factor and a rectification ratio of ∼10 6 . The electron beam-induced current measurement confirms the junction position. The extracted minority carrier diffusion length is much higher compared to those previously reported, suggesting a low surface recombination velocity in these lateral NWp-n diodes., (© 2021 IOP Publishing Ltd.)

Despite the strong interest in optoelectronic devices working in the deep ultraviolet range, no suitable low cost, large-area, high-quality AlN substrates have been available up to now. The aim of this work is the selective area growth of AlN nanocolumns by plasma assisted molecular beam epitaxy on polar (0001) and semi-polar (11–22) GaN/sapphire templates. The resulting AlN nanocolumns are vertically oriented with semi-polar {1–103} top facets when grown on (0001) GaN/sapphire, or oriented at 58° from the template normal and exposing {1–100} non-polar top facets when growing on (11–22) GaN/sapphire, in both cases reaching filling factors ≥80%. In these kinds of arrays each nanostructure could function as a building block for an individual nano-device or, due to the large filling factor values, the overall array top surfaces could be seen as a quasi (semi-polar or non-polar) AlN pseudo-template. [ABSTRACT FROM AUTHOR]

Experimental data and a model are presented which define the boundary values of V/III flux ratio and growth temperature for droplet-assisted nucleation of InAs semiconductor nanowires in selective-area epitaxy on SiOx/Si (111) substrates by molecular beam epitaxy. Within these boundaries, the substrate receives a balanced flux of group III and V materials allowing the growth of vertically oriented nanowires as compared to the formation of droplets or crystallites. [ABSTRACT FROM AUTHOR]