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Herein, we present an electrochemical functionalization strategy for high quality single-layer and multilayer chemical vapor deposited (CVD) graphene directly on a Si/SiO2 chip facilitating electronic interfacing. This method avoids oxidation and tearing of graphene basal planes. We demonstrate effective functionalization by D-(+)-biotin (Bio), 4-(phenyldiazenyl)-aniline (Dz), and gallic acid (Gall) using cyclic voltammetry. Raman spectroscopy and XPS are used to demonstrate effective functionalization. In order to evaluate the effect of the electrochemical functionalization on graphene properties, DC electrical conductivity, XPS, mobility, and carrier density analysis are presented. We show that this functionalization strategy does not degrade graphene mobility (103 cm2 V-1s-1). After functionalization we observe a rise in Fermi level of ∼0.06 eV. In addition, we prove sensing capabilities with a CVD graphene monolayer on the biotin/avidin system by electrical resistance measurements and electrochemical impedance spectroscopy reaching a detection of 2.5 ng ml-1. This paper demonstrates an effective strategy to functionalize high quality CVD graphene on a chip compatible with an electronic interface readout.

A quantitative analysis of blurring and its dependence on the stencil-substrate gap and the deposition parameters in stencil lithography, a high resolution shadow mask technique, is presented. The blurring is manifested in two ways: first, the structure directly deposited on the substrate is larger than the stencil aperture due to geometrical factors, and second, a halo of material is formed surrounding the deposited structure, presumably due to surface diffusion. The blurring is studied as a function of the gap using dedicated stencils that allow a controlled variation of the gap. Our results show a linear relationship between the gap and the blurring of the directly deposited structure. In our configuration, with a material source of approximately 5 mm and a source-substrate distance of 1 m, we find that a gap size of approximately 10 microm enlarges the directly deposited structures by approximately 50 nm. The measured halo varies from 0.2 to 3 microm in width depending on the gap, the stencil aperture size and other deposition parameters. We also show that the blurring can be reduced by decreasing the nominal deposition thickness, the deposition rate and the substrate temperature.

The hydrogen sensing characteristics of a single nanotrench fabricated by focused ion beam milling (FIB) in an evaporated palladium microwire are presented. In situ atomic force microscopy (AFM) measurements proved that, in the presence of H(2), the trench closes and electrically connects the initially separated parts of the wire due to the increase in volume of the material. Therewith, an electrical current can be switched through the wire. With experiments under various H(2) concentrations and a mathematical model, we describe the closing mechanism of the trench with respect to various parameters, including the substrate material, film thickness, trench size and wire dimensions. Results have been compared with those from equivalent continuous wires. Thin SiO(2) and polyimide (PI) layers on silicon were used to study the effect of substrate elasticity. Sufficient lateral expansion of Pd to close trenches of up to 70 nm in width has only been observed on PI, which we attribute to its advantageous elastic properties. The scale of the response times allowed the observation of two superposing effects: the chemical conversion of Pd to PdH(x) and the mechanical closing of the trench.

We propose a new process for forming parallel nanobridge patterns by nanostencil lithography. In this process, a low-stress silicon nitride stencil with parallel nanobridge structures is fabricated by a new edge patterning technique where those nanobridges are formed simultaneously via sidewall features using the conventional photolithography and anisotropic dry etching process. After forming primary Cr patterns on the oxidized Si substrate by depositing Cr through the edge-patterned stencil, those patterns are transferred onto the underlying Si layer in a reversed manner, leading to the formation of parallel Cr nanobridge patterns on the Si substrate. Using this process, we have successfully produced 85 nm-wide parallel Cr nanobridge patterns from a stencil with 115 nm-wide nanobridge structures that was fabricated by conventional microlithography. As there is no need for advanced lithography techniques in preparing the nanobridge stencil, the combination of the edge patterning and reverse nanostencil process provides a cost-effective tool for the massive fabrication of parallel nanobridge arrays at the 100 nm scale.