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As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfOx)-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks. [ABSTRACT FROM AUTHOR]

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiOx/Al2O3-based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer. [ABSTRACT FROM AUTHOR]

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiO x /Al 2 O 3 -based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer., (© 2021 IOP Publishing Ltd.)

SiN x -based nano-structure resistive memory is fabricated by fully silicon CMOS compatible process integration including particularly designed anisotropic etching for the construction of a nano-cone silicon bottom electrode (BE). Bipolar resistive switching characteristics have significantly reduced switching current and voltage and are demonstrated in a nano-cone BE structure, as compared with those in a flat BE one. We have verified by systematic device simulations that the main cause of reduction in the performance parameters is the high electric field being more effectively concentrated at the tip of the cone-shaped BE. The greatly improved nonlinearity of the nano-cone resistive memory cell will be beneficial in the ultra-high-density crossbar array.