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In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors's knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices., (© 2023 IOP Publishing Ltd.)

In this study, we present a runtime reconfigurable nanomagnetic (RRN) adder design offering significant area efficiency and high speed operations. Subsequently, it is implemented using a micromagnetic simulation tool, by exploiting the reversal magnetization and energy minimization nature of the nanomagnets. We compute the carry and sum of the 1-bit full adder using only two majority gates comprising a total of 7 nanomagnets and single design layout. Consequently, the on-chip clocking schematic for the proposed RRN adder implementation for both horizontal and vertical layouts are introduced. The quantitative analysis of the required resources for higher bit adder architecture using the proposed design is performed and compared with state-of-the art. The proposed design methodology leads to ∼86%, ∼83% and ∼93% reduction in the number of nanomagnets, majority gates and clock cycles respectively resulting in an area efficient and high speed RRN adder architecture.

In this paper, we propose a dipole coupled magnetic quantum-dot cellular automata-based approximate nanomagnetic (APN) architectural design approach for subtractor and adder. In addition, we also introduce an APN architecture which offers runtime reconfigurability using a single design layout comprising only four nanomagnets. Subsequently, we propose the APN add/sub architecture by exploiting shape anisotropy and ferromagnetically coupled fixed input majority gate. The proposed APN architecture designs have been implemented using a micromagnetic simulation tool and performance has been compared with the state-of-the-art approach resulting in a ∼50%-80% reduction in the number of nanomagnets and clock cycles without degradation in the accuracy leading to area and energy efficiency.

In this letter, we introduce the magnetic quantum-dot cellular automata (MQCA) based area and speed efficient design approach for nanomagnetic full adder implementation. We exploited the physical properties of three input MQCA majority gate (MG), where the fixed input of the MG is coupled ferromagnetically to one of the primary input operands. Subsequently we propose a design methodology, mapping logic and micromagnetic software implementation, validation of the binary full adder architecture built using two-three inputs MQCA MGs. In addition, we also analyzed our proposed design for switching errors to ensure bit stability and reliability. Our proposed design leads to ∼36%-69% reduction in the number of nanomagnets, ∼50%-75% reduction in the number of clock cycles and ∼33%-50% reduction in the number of MG operations required for the binary full adder implementation compared to the state of art designs.