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We demonstrate a hybrid process for fabricating one-dimensional wire devices. The process is a combination of an alignment procedure using dielectrophoresis and subsequent contact metal formation utilizing electrochemical deposition with non-toxic organic-based Au electrolytes. Several devices have been successfully made from GaN nanowires or multi-walled carbon nanotubes (MWCNTs) using our hybrid technique. We demonstrate that rapid thermal annealing improves the ohmic characteristics by five orders of magnitude in the case of the GaN devices and [?]300% in the case of the MWCNT devices. One of the reasons for this improvement is enhanced gold wetting due to the reduction of grain size at the annealing temperature. [ABSTRACT FROM AUTHOR]

A graphene-MoS 2 (GM) heterostructure based diode is fabricated using asymmetric contacts to MoS 2 , as well as an asymmetric top gate (ATG). The GM diode exhibits a rectification ratio of 5 from asymmetric contacts, which is improved to 10 5 after the incorporation of an ATG. This improvement is attributed to the asymmetric modulation of carrier concentration and effective Schottky barrier height (SBH) by the ATG during forward and reverse bias. This is further confirmed from the temperature dependent measurement, where a difference of 0.22 eV is observed between the effective SBH for forward and reverse bias. Moreover, the rectification ratio also depends on carrier concentration in MoS 2 and can be varied with the change in temperature as well as back gate voltage. Under laser light illumination, the device demonstrates strong opto-electric response with 100 times improvement in the relative photo current, as well as a responsivity of 1.9 A W -1 and a specific detectivity of 2.4 × 10 10 Jones. These devices can also be implemented using other two dimensional (2D) materials and suggest a promising approach to incorporate diverse 2D materials for future nano-electronics and optoelectronics applications.

We demonstrate silicon germanium (SiGe) alloy nanowires (NWs) with Ge nanoparticles (GeNPs) embedded in a SiO2 shell as a material for decreasing thermal conductivity. During thermal oxidation of SiGe NWs to form SiGe-SiO2 core-shell structures, Ge atoms were diffused into the SiO2 shell to relax the strain in the SiGe core, and agglomerated as a few nanometer-sized particles. This structure leads to a large reduction in thermal conductivity due to the GeNP-phonon interaction, while electrical conductivity is sustained because the core of the SiGe alloy NW provides a current path for the charged carriers. The thermal conductivity of the SiGe alloy NWs wrapped with a GeNP-embedded SiO2 shell is 0.41 W m(-1) K(-1) at 300 K.

Graphene growth on a copper surface via metal-catalyzed chemical vapor deposition has several advantages in terms of providing high-quality graphene with the potential for scale-up, but the product is usually inhomogeneous due to the inability to control the graphene layer growth. The non-uniform regions strongly affect the reliability of the graphene in practical electronic applications. Herein, we report a novel graphene transfer method that allows for the selective exfoliation of single-layer graphene from non-uniform graphene grown on a Cu foil. Differences in the interlayer bonding energy are exploited to mechanically separate only the top single-layer graphene and transfer this to an arbitrary substrate. The dry-transferred single-layer grapheme showed electrical characteristics that were more uniform than those of graphene transferred using conventional wet-etching transfer steps.

We successfully fabricated ferroelectric-gate field effect transistor (FEFET)-based nonvolatile memory devices using an n-type Si nanowire coated with omega-shaped-gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene) via a low-temperature fabrication process. Our FEFET memory devices with controllable threshold voltage via adjustment of the doping concentration exhibit excellent memory characteristics with ultra-low ON state power dissipation (≤3 nW), a large modulation in channel conductance between the ON and OFF states exceeding 10(5), a long retention time of over 3 × 10(4) s and a high endurance of over 10(5) programming cycles whilst maintaining an I ON/I OFF ratio higher than 10(3). This result may be promising for next-generation nonvolatile memory on flexible substrate applications.