Search

As the trajectory of transistor scaling defined by Moore's law encounters challenges, the paradigm of ever-evolving integrated circuit technology shifts to explore unconventional materials and architectures to sustain progress. Two-dimensional (2D) semiconductors, characterized by their atomic-scale thickness and exceptional electronic properties, have emerged as a beacon of promise in this quest for the continued advancement of field-effect transistor (FET) technology. The energy-efficient complementary circuit integration necessitates strategic engineering of both n-channel and p-channel 2D FETs to achieve symmetrical high performance. This intricate process mandates the realization of demanding device characteristics, including low contact resistance, precisely controlled doping schemes, high mobility, and seamless incorporation of high- κ dielectrics. Furthermore, the uniform growth of wafer-scale 2D film is imperative to mitigate defect density, minimize device-to-device variation, and establish pristine interfaces within the integrated circuits. This review examines the latest breakthroughs with a focus on the preparation of 2D channel materials and device engineering in advanced FET structures. It also extensively summarizes critical aspects such as the scalability and compatibility of 2D FET devices with existing manufacturing technologies, elucidating the synergistic relationships crucial for realizing efficient and high-performance 2D FETs. These findings extend to potential integrated circuit applications in diverse functionalities. [ABSTRACT FROM AUTHOR]

The rice husk (RH) combustion pretreatment method plays a crucial role in the extraction of nanoscale SiO2 from RH as a silicon source. This study examined the effects of diverse pretreatment methods and combustion temperatures on the particle size distribution of nanoscale high-purity amorphous SiO2 extracted from rice husk ash (RHA) post RH combustion. The experiment was structured using the Taguchi method, employing an L9 (21 × 33) orthogonal mixing table. The median diameter (D50) served as the output response parameter, with the drying method (A), combustion temperature (B), torrefaction temperature (C), and pretreatment method (D) as the input parameters. The results showed the torrefaction temperature (C) as being the predominant factor affecting the D50, which decreased with an increasing torrefaction temperature (C). The optimal parameter combination was identified as A2B2C3D2. The verification test revealed that roasting could improve the abrasiveness of Rh-based silica and reduce the average particle size. Torrefaction at medium temperatures might narrow the size distribution range of RHA-SiO2. We discovered that the purity of silica increased with an increasing roasting temperature by evaluating the concentration of silica in the sample. The production of RHA with silica concentrations up to 92.3% was investigated. X-ray diffraction analysis affirmed that SiO2's crystal structure remained unaltered across different treatment methods, consistently presenting as amorphous. These results provide a reference for extracting high-value products through RH combustion. [ABSTRACT FROM AUTHOR]

Synthesis of the vertically aligned carbon nanotubes (CNTs) using complementary metal-oxide-semiconductor (CMOS)-compatible methods is essential to integrate the CNT contact and interconnect to nanoscale devices and ultra-dense integrated nanoelectronics. However, the synthesis of high-density CNT array at low-temperature remains a challenging task. The advances in the low-temperature synthesis of high-density vertical CNT structures using CMOS-compatible methods are reviewed. Primarily, recent works on theoretical simulations and experimental characterizations of CNT growth emphasized the critical roles of catalyst design in reducing synthesis temperature and increasing CNT density. In particular, the approach of using multilayer catalyst film to generate the alloyed catalyst nanoparticle was found competent to improve the active catalyst nanoparticle formation and reduce the CNT growth temperature. With the multilayer catalyst, CNT arrays were directly grown on metals, oxides, and 2D materials. Moreover, the relations among the catalyst film thickness, CNT diameter, and wall number were surveyed, which provided potential strategies to control the tube density and the wall density of synthesized CNT array. [ABSTRACT FROM AUTHOR]

A method to synthesize high-density, vertically-aligned, multi-wall carbon nanotubes (MWCNTs) on an insulating substrate at low temperature using a complementary metal–oxide–semiconductor (CMOS) compatible process is presented. Two factors are identified to be important in the carbon nanotube (CNT) growth, which are the catalyst design and the substrate material. By using a Ni–Al–Ni multilayer catalyst film and a ZrO2 substrate, vertically-aligned CNTs can be synthesized at 340 °C using plasma-enhanced chemical vapor deposition (PECVD). Both the quality and density of the CNTs can be enhanced by increasing the synthesis temperature. The function of the aluminum interlayer in reducing the activation energy of the CNT formation is studied. The nanoparticle sintering and quick accumulation of amorphous carbon covering the catalyst can prematurely stop CNT synthesis. Both effects can be suppressed by using a substrate with a high surface energy such as ZrO2. [ABSTRACT FROM AUTHOR]