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In this paper, a new method is proposed for recognizing rotated objects based on extracted feature points from the Harris corner detector using object corner points at real time in a mobile environment. With this proposed method, corner points can be rapidly extracted from the input image and object recognition can be conducted by comparing existing feature points. Color values for corner pixels in the feature points of rotated objects are generally varied in accordance with the degree of object rotation. The color values of the feature points are affected by the degree of rotated objects; therefore, there is a possibility that these values can be mixed with nearby pixel values. By analyzing the color values of the rotated pixels, we can extract feature points of rotated objects and use them for object detection to be effectively applied for rotated object detection. Although overall recognition rate is somewhat degraded, using the proposed object recognition with corner information of feature points makes it possible to execute in real time in mobile environments by reducing the amount of computation. Accordingly, this method can be applied to recognizing rotated objects, even in a mobile environment with limited computing capabilities. Experimental results show that the proposed method can provide approximately 96 % accuracy and high performance compared to other methods. Therefore, the proposed method can be adapted to recognize any rotated object with performance and accuracy.

The main purpose of this research is to design a new memory architecture for NAND flash memory to provide XIP (execute in place) for code execution as well as overcome the biggest bottleneck for data execution. NOR flash for multimedia application is particularly well suited for code storage and execute-in-place (XIP) applications, which requires high-speed random access. While NAND flash provides high density and low cost data storage, it is not applicable to XIP applications due to the page access and long access latency. To overcome these limitations, NAND flash can be exploited as code memory for XIP by using SDRAM/SRAM buffer. In order to design the code memory, we proposed a NAND flash with a dual instruction buffer. Furthermore, another enhancement was proposed for the overall system performance by applying a data buffer system to the existing NAND flash memory to reduce the number of write and erase operations; otherwise which could be the biggest bottleneck in a flash memory system. In conclusion, the proposed NAND flash buffer system based on Harvard architecture is operated as main memory as well as the lowest storage device for mobile multimedia system. According to our simulation results, write and erase operations are approximately 60 % and 68 % less than other unified buffer systems, respectively, with two times more space. In addition, the average memory access time is improved by approximately 75 % compared with other unified buffer systems.

For the ubiquitous computing environment, an important assumption is that all the components in any specific environment are connected with each other. With this assumption, we introduce an effective scheme to provide a personalized service based on Virtual Personal World (VPW). Virtual Personal World (VPW) which is a model focused on service continuity with specially designed components. Previous ubiquitous frameworks have been concerned with the location where a user is provided any specific service. However those questions above are not the most important problems anymore in VPW. It concentrates on the point whether the services are successive or not, wherever a user goes to any place. Services are not regarded as a sum of functions which is embedded on any objects in any certain place. We conceptually define a resource management scheme based on a unified form of the object which participates in service provision, so called virtual object (VO). Thus the service can be described as the sum of functions of VOs. With our resource management scheme, users can utilize their required object as VO wherever it is located. And also, for better utilization of VPW service, we introduce a novel form of profiles and service provision scheme based on the polymorphism. Our simulation result shows that the Ratio of VPW pure service time is 0.15 % higher than conventional location based service. And also the possibility that users can meet adequate service he wants raised 29 % in our proposed VPW environment.

In this study, an object contour tracking method is proposed for an object with large motion and irregular shape in image sequence. To track object contour accurately, an active contour model was used, and the initial snake point of the next frame is set by defining feature points with changing curvature in the object tracked from the previous frame and calculating an optical flow at the location. Here, any misled optical flow due to irregular changes in shape or fast motion was filtered by producing a difference edge map from the previous frame, and as a solution to the energy shortage of objects with complex contour, a method of adding snake points by partial curvature was applied. Findings from experiments with real image sequence showed that the contour of an object with large motion and irregular shapes was extracted in a relatively precise way.

Multimedia system-on-a-chip (SoC) platform designs nowadays are facing some conflicting issues regarding product development. One is induced by increasing design complexity and another is induced by decreasing time-to-market. Hence, designers are seeking a more efficient and reliable methodology in order to design complex multi-million gate SoC under such harsh conditions. In particular, the complexity of a generic pin control block in multimedia SoC which implements input/output (I/O) paths for off-chip communication has increased exponentially in recent years. Accordingly, the possibility of introducing human errors in designing such block has grown. Operation of generic-pin control block needs to be validated with a top-level RTL from the early stages of design, which correctly checks full-chip interface. However, generic-pin control block has inherent several design issues since function registers and multi-I/O paths are usually fixed in the relatively late stages of design. Also, the role of a generic pin control block that shares limited pins causes frequent changes in pin assignment. Therefore, current design approaches of a generic pin control block are no longer adequate to meet the challenges of design productivity, design reusability, and shorter time-to-market for design. And, this results in many possible human errors when using a traditional RTL description. As a response to this problem, this paper presents a design automation based approach to reduce the possibility of human errors. In the case study presented, we succeeded in auto-generating a generic pin control block in multimedia SoC platforms which has more than 300 general purpose I/O interfaces including both input and output, as well as 900 PAD pins. Ultimately, we reduced the amount of manual description for generating a generic pin control block by a whopping 97 %.

Detection of facial feature is fundamental for applications such as security, biometrics, 3D face modeling and personal authentication. Active Shape Model (ASM) is one of the most popular local texture models for face detection. This paper presents an issue related to face detection based on ASM, and proposes an efficient extraction algorithm for facial landmarks suitable for use on mobile devices. We modifies the original ASM to improve its performance with three changes; (1) Improving the initialization model using the center of the eyes by using a feature map of color information, (2) Constructing modified model definition and fitting more landmarks than the classical ASM, and (3) Extending and building a 2-D profile model for detecting faces in input image. The proposed method is evaluated on dataset containing over 700 images of faces, and experimental results reveal that the proposed algorithm exhibited a significant improvement of over 10.2 % in average success ratio, compared to the classic ASM, clearly outperforming on success rate and computing time.

A noteworthy thing in desktop PCs is that they can provide a great opportunity to increase the performance of processing multimedia data by exploiting task- and data-parallelism with multi-core CPU and many-core GPU. This paper presents a high performance parallel implementation of 2D DCT on this heterogeneous computing environment. For this purpose, Intel TBB (threading building blocks) and OpenCL (Open Compute Language) are utilized for task- and data-parallelism, respectively. The simulation result shows that the parallel DCT implementations far the serial ones in processing speed. Especially, OpenCL implementation shows a linear speedup, a typical SIMD characteristic as the increase of 2D data sets.

The rapid advance of computer hardware and popularity of multimedia applications enable multi-core processors with sub-word parallelism instructions to become a dominant market trend in desk-top PCs as well as high end mobile devices. This paper presents an efficient parallel implementation of 2D convolution algorithm demanding high performance computing power in multi-core desktop PCs. It is a representative computation intensive algorithm, in image and signal processing applications, accompanied by heavy memory access; on the other hand, their computational complexities are relatively low. The purpose of this study is to explore the effectiveness of exploiting the streaming SIMD (Single Instruction Multiple Data) extension (SSE) technology and TBB (Threading Building Block) run-time library in Intel multi-core processors. By doing so, we can take advantage of all the hardware features of multi-core processor concurrently for data- and task-level parallelism. For the performance evaluation, we implemented a 3?×?3 kernel based convolution algorithm using SSE2 and TBB with different combinations and compared their processing speeds. The experimental results show that both technologies have a significant effect on the performance and the processing speed can be greatly improved when using two technologies at the same time; for example, 6.2, 6.1, and 1.4 times speedup compared with the implementation of either of them are suggested for 256?×?256, 512?×?512, and 1024?×?1024 data sets, respectively.