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Results presented here indicate a strong dependence between the surface roughness and its uniformity of epitaxial layers grown by chemical vapor deposition (CVD) and the underlying substrate dislocations and its domain structure. The substrates used were cut from boules grown by physical vapor deposition (PVT). The facet area and its borders were found to impact the CVD grown epitaxial layers. Epitaxial layers, 50 µm thick, were grown on 8° off-axis substrates. Substrates with and without micropipes were selected in order to investigate their impact on the epitaxy. Both wafers indicate a correlation between etch pit dislocation (EPD) density and surface roughness. However, the in general lower EPD density in the micropipe free wafer enhances the variation in surface roughness between different regions. The micropipe free substrate has an EPD equal to 1.3×104 cm−2 in the facet region, and the surface roughness, Ra, is 1.0 nm (2.98×2.32 mm2 area), while there is an increase both in EPD density and surface roughness in the close proximity corresponding to the border around the facet. Also thick epitaxial layers, 30 µm thick, were grown on near on-axis substrates, both C-face and Si-face, in order to investigate how the surface morphology develops with less influence from the step-flow growth mechanism. Both crystal directions are characterized by a three dimensional growth front surface similar as for PVT grown crystals in the facet region. The mix between step-flow and dislocation driven growth on near on-axis C-face chemical vapor deposition (CVD) grown epi-layers is resulting in a as smooth, and measured surface roughness is as low as for growth on 8° off-axis substrates.

It is well-known that SiC crystal deficiencies are delaying the realization of outstandingly superior SiC power electronics. Efforts to date have centered on eradicating micropipes, and 4H-SiC substrates with extremely low micropipe densities have been achieved. Nevertheless, SiC substrates and epilayers still contain several types of dislocations in densities on the order of thousands per square centimetres, which are nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has recently been demonstrated that dislocations existing in SiC crystals degrade several characteristics of SiC devices, e.g., the forward bias characteristics of SiC pin diodes and the gate oxide reliability of SiC MOSFETs.This paper reports several dislocation processes occurring during the growth of hexagonal SiC bulk crystals. Particularly, we focus on the dislocation formation and propagation processes in SiC crystals. We have investigated dislocation processes in 4H-SiC bulk crystals grown by the physical vapor transport (PVT) growth method, using defect selective etching and transmission electron microscopy (TEM).It was found that foreign polytype inclusions introduced a high density of dislocations at the polytype boundary. In the polytype-transformed areas of the crystal, very few medium size hexagonal etch pits due to threading screw dislocations were observed, indicating that the polytype transformation ceased the propagation of threading screw dislocations. The oval-shaped etch pit arrays observed on the etched vicinal (0001)Si surface, indicative of the dislocation multiplication in the basal plane, showed characteristic distribution around micropipes and low angle grain boundaries. Based on the results, we will argue the dislocation behavior in PVT grown SiC crystals, suggesting that dislocation interaction and conversion are relevant processes to understanding the behavior.

II-VI, Inc. is a commercial supplier of high-quality SiC substrates (including 2-inch and 3-inch diameter) for RF and power applications to the US market. Semi-insulating 6H-SiC single crystals, doped with vanadium and undoped (vanadium-free), as well as ntype 4H crystals have been grown using the PVT and Advanced PVT (APVT) growth techniques. The APVT process incorporates insitu synthesis and growth of of SiC crystal from Si and C precursors.Grown 6H-SiC and 4H-SiC crystals have been extensively characterized with respect to their purity, crystal quality and electrical properties. COREMA resistivity maps demonstrate that V-compensated boules exhibited axially and radially uniform resistivity around 1011 ω.cm at room temperature. Undoped (V-free) wafers contained residual boron and nitrogen at levels below 1016 atoms/cm3, and demonstrated semi-insulating properties (resistivity between 106 and 1011 ω.cm) as a result of compensation by native point defects with deep levels in the bandgap. The undoped semi-insulating crystals grown by APVT contained boron and nitrogen at 1.9ω1015 cm−3 and 3.8.1015 cm−3, respectively.High-quality 2-inch SiC wafers exhibited micropipe densities on the order of 10 cm−2 and dislocation density on the order of 104 cm−2.

A method is presented for detecting, counting and mapping micropipes and dislocations in n+, undoped, and semi-insulating Silicon Carbide wafers. The technique is based on etching in molten Potassium Hydroxide (KOH), and it employs image processing that automatically detects etch pits, discriminates between micropipes and dislocations, and generate micropipe and dislocation density maps. We demonstrate a novel way of detecting and mapping dislocations and micropipes in semi-insulating SiC. This is achieved by combining a properly tuned etching technique that reliably produces well defined etch pits with image processing that enables quick and accurate analysis of the etch pit contrast. We show that the results of optical evaluation are close to those obtained using the Synchrotron White Beam X-Ray Topography (SWBXT) technique.

The performance enhancements offered by the next generation of SiC high power devices offer potential for enormous growth in SiC power device markets in the next few years. For this growth to occur, it is imperative that substrate and epitaxial material quality increases to meet the needs of the targeted applications. We will discuss the status and requirements for SiC substrates and epitaxial material for power devices such as Schottky and PiN diodes. For the SiC Schottky device where current production is approaching 50 amp devices, there are several material aspects that are key. These include; wafer diameter (3-inch and 100-mm), micropipe density (−2 for 3-inch substrates and 16 cm−2 for 100-mm substrates), epitaxial defect densities (total electrically active defects −2), epitaxial doping and epitaxial thickness uniformity. For the PiN diodes the major challenge is the degradation of the Vf characteristics due to the introduction of stacking faults during the device operation. We have demonstrated that the stacking faults are often generated from basal plane dislocations in the active region of the device. Additionally we have demonstrated that by reducing the basal plane dislocation density, stable PiN diodes can be produced. At present typical basal plane dislocation densities in our epitaxial layers are 100 to 500 cm−2; however, we have achieved basal plane dislocation densities as low as 4 cm−2 in epitaxial layers grown on 8° off-axis 4H-SiC substrates.

The density and distribution of micropipes (MPD's), a screw dislocation with a hollow core, are significant criteria for SiC wafer selection in device fabrication. For this reason the measurement of micropipes in SiC is an important problem. The micropipe distributions of 2’’ diameter 6H SiC wafers from three different PVT furnace designs in three different laboratories were statistically characterized. The micropipe distributions were measured in two ways: by KOH etching the wafer and then counting the hexagonal pits formed on the wafer surface using a microscope and imaging software; and by manually counting with an optical transmission microscope the micropipes on a un-etched wafer within a grid of 0.5mm squares superimposed over the wafer. None of the wafers had a random distribution of micropipes i.e. they did not follow a Poisson distribution. The micropipes were found to associate with each other i.e. there is a higher probability of there being other micropipes near a location where a micropipe has been found. In the eight samples characterized, 1.9% of the wafer area contained 32% of the total micropipes. We have analyzed the repeatability of the optical transmission microscopy method of micropipe characterization and found that it is dependent on the micropipe density; the standard deviation of the measurement increases with increasing MPD. The number of micropipes counted increases by about 10% with increasing magnification and 15% when the wafer is double side polished.

High Power asymmetric SiC GTOs (Gate Turn-Off Thyristors) were fabricated on n-type 4H-SiC substrates with multiple epi-layers and were tested to investigate breakdown voltage, maximum current density, switching characteristics, and temperature dependences.Comparison of breakdown voltages achieved by GTOs with Guard Ring edge termination and GTOs with a proprietary Junction Termination Extension (JTE) fabricated on the same wafer are made. Individual GTOs with a nominal area of 4 mm2 (2 mm × 2 mm) utilizing the JTE were tested in forward bias and found to support over 6 kV at leakage currents of less than 5 μA. In addition, GTOs with a nominal area of 0.25 mm2 (0.5 mm × 0.5 mm) utilizing the JTE were found to support over 7 kV. These blocking voltages are the highest reported for GTOs in SiC. [1–5] Wafer maps of the breakdown voltages for older and newer wafers suggest an improvement of the material. The defect density for the newer wafer is estimated to be greater than the micropipe density.The on-state characteristics are equally impressive, with 4 mm2 GTOs carrying > 1000 A/cm2. The GTO has a forward voltage drop of 3.66 V at a current density of 300 A/cm2 at room temperature and a forward voltage drop of 3.1 V at 300 A/cm2 at 224 °C. This indicates that on-state losses should not be excessive, even at high current densities and high temperatures.

Numerical simulations of the thermal stress distribution in a SiC boule 2” in diameter and 1” long grown by conventional PVT technique were performed based on the temperature field distribution in a resistively heated growth reactor that was simulated using the GAMBIT-2.0.4/FIDAP-8.6.2 software package. Analysis of the simulation results revealed the existence of a thermal stress, which was excessively nonuniform in distribution and whose magnitude exceeded the value of the critical resolved shear stress of 1.0 MPa by a factor of 2. The high stress initiated plastic deformation and the high temperature provoked the intense self-diffusion processes. The combination of these factors alters the mechanism of plastic deformation, significantly affecting the structural quality of the growing crystal. The influence of self-diffusion processes initiating the formation of interstitial atoms and vacancies; stacking fault formation as a result of the nonconservative motion of the basal plane dislocations; and micropipe formation from the dislocation groups piled up at silicon and carbon second phase inclusions are also discussed.

Homoepitaxial growth, impurity doping, and diode fabrication on 4H-SiC(11–20) and (03–38) have been investigated. Although the efficiency of nitrogen incorporation is higher on the non-standard faces than on (0001), a low background doping concentration of 2∼3×1014 cm-3 can be achieved. On these faces, boron and aluminum are less effectively incorporated, compared to the growth on off-axis (0001). 4H-SiC(11–20) epilayers are micropipe-free, as expected. More interestingly, almost perfect micropipe closing has been realized in 4H-SiC (03–38) epitaxial growth. Ni/4H-SiC(11–20) and (03–38) Schottky barrier diodes showed promising characteritics of 3.36 kV-24 mΩcm2 and 3.28 kV–22 mΩcm2, respectively. The breakdown voltage of 4H-SiC(03–38) Schottky barrier diodes was significantly improved from 1 kV to above 2.5 kV by micropipe closing.

The objective of this work is to study defect occurrence and appearance in thick sublimation epitaxial layers grown on top of LPE layers with different thickness and substrates with reduced micropipe density. Data from growth on C-terminated surfaces are also presented. The results were analyzed with the aid of optical microscopy, SEM images, HRXRD and synchrotron white beam X-ray topography. A pronounced effect of the LPE (buffer) layer surface roughness on formation of dislocations and micropipes is observed in the sublimation epitaxy layers. While with increasing the thickness of the buffer layer the efficiency of the micropipe reduction increases, the structure quality of the top sublimation epilayer degrades. LPE layers with a thickness of 0.1 μm appear to be the best compromise.

To reduce the defect density inherent in conventional heteroepitaxial growth of SiC on Si, selective epitaxy followed by lateral epitaxial growth was performed in a conventional atmospheric pressure chemical vapor deposition (APCVD) system. The source gas was primarily hexamethyldisilane (HMDS). Hydrogen was used as the carrier gas and small amounts of hydrogen chloride (HCl) were added to improve the selectivity. Si(001) wafers, with an oxide layer (∼ 700 nm thick) as a mask, were used as substrates. The grown films were analyzed using optical microscopy and scanning electron microscopy (SEM). In earlier work, we had demonstrated the problems associated with the application of this technique – viz., oxide degradation and high growth temperature. Using HMDS, the growth temperature has been considerably reduced allowing the continued use of an oxide mask. Selective growth was demonstrated in films grown at 1250° and below.

The status of SiC vapor growth technique (PVT) is reviewed and related innovative aspects are introduced. Problems of the preparation of SiC crystals with uniform electronic properties are addressed, especially the growth of semiinsulating SiC. An overview about the performance of numerical modeling is given as tool for the optimization of the PVT process. Development activities in the field of liquid phase processing for the preparation of SiC bulk crystals and micropipe healing are presented. Finally recent results on the present understanding of filamentary void formation/elimination (micropipes, macrodefects) are summarized.

A layer of porous SiC was fabricated by surface anodization of commercial 4H and 6H-SiC (0001)Si face off-axis wafers. A 8.5 μm 4H–SiC epilayer was grown on porous SiC (PSC) substrates using atmospheric pressure CVD. TEM investigation on cross-sectional specimens of the CVD epitaxial layers revealed that the presence of pores in the substrate does not lead to the formation of any micropipe in the epitaxial layer. The investigation also failed to detect a more than usual dislocation density on the basal plane of the epitaxial layer. Based upon the results of various analytical techniques applied to the CVD deposit we propose that the density of screw dislocations in the epitaxial layer is less than 5–104 cm−3. It should be noted that the density of similar types of dislocations in the initial substrate as determined by the TEM was ∼106 cm−3, so this preliminary investigation indicates that the epitaxial layer grown on PSC may have a reduction in dislocation density of more than an order of magnitude over those grown on conventional SiC substrates that are not porous. Synchrotron white beam x-ray topography (SWBXT) was performed on these layers. Comparison between the dislocation density on the porous and standard epitaxial layers proved to be very similar using this technique.

SiC is an important wide bandgap semiconductor material for high temperature and high power electronic device applications. Purity improvements in the growth environment has resulted in a two-fold benefit during growth: (a) minimized inconsistencies in the background doping resulting in high resistivity (>5000 ohm-cm) wafer yield increase from 10–15% to 70-85%, and (b) decrease in micropipe formation. Growth parameters play an important role in determining the perfection and properties of the SiC crystals, and are extremely critical in the growth of large diameter crystals. Several aspects of growth are vital in obtaining highly perfect, large diameter crystals, such as: (i) optimized furnace design, (ii) high purity growth environment, and (iii) carefully controlled growth conditions. Although significant reduction in micropipe density has been achieved by improvements in the growth process, more stringent device requirements mandate further reduction in the defect density. In-depth understanding of the mechanisms of micropipe formation is essential in order to devise approaches to eliminate them. Experiments have been performed to understand the role of growth conditions and ambient purity on crystal perfection by intentionally introducing arrays of impurity sites on one half of the growth surface. Results clearly suggest that presence of impurities or second phase inclusions during start or during growth can result in the nucleation of micropipes. Insights obtained from these studies were instrumental in the growth of ultra-low micropipe density (less than 2 micropipes cm−2 ) in 1.5 inch diameter boules.

Micro/nanopipes are linear defects along the c-axis of hexagonal polytypes of SiC and GaN that are currently the focus of much attention. It has been shown that these defects can be very detrimental to the electronic properties of devices manufactured from, at least, 6H-SiC. In this paper, the origin of these defects is discussed in terms of Frank's theory [1] that dislocations will have a hollow core when their Burgers vector is large. Two fundamental issues about such dislocations are addressed: their formation along the c-axis of the crystal, and their stability despite their large Burgers vectors [2]. The proposed model is based on the mosaic structure of sublimation-grown 6H- or 4H-SiC, and VPE-grown 2H-GaN on sapphire substrates. The presence of unit c-axis screw dislocations is attributed to the accommodation of low-angle twist boundaries in the mosaic structure. The formation of superscrew dislocations with large Burgers vector, which empty their cores to reduce the excessive strain energy there, is shown to be the result of 3c screw dislocations in the axis of triple junctions which “getter” the neighboring unit dislocations and simultaneously increase their diameter. The predictions of the model are compared with available data in the literature, and suggestions are made for the decrease of nano/micropipe density.

The defect formation during sublimation bulk crystal growth of silicon carbide (SiC) is discussed. SiC bulk crystals are produced by seeded sublimation growth (modified-Lely method), where SiC source powder sublimes and is recrystallized on a slightly cooled seed crystal at uncommonly high temperatures (≥2000°C). The crystals contain structural defects such as micropipes (hollow core dislocations), subgrain boundaries, stacking faults and glide dislocations in the basal plane. The type and density of the defects largely depend on the crystal growth direction, and many aspects are different between the growth parallel and perpendicular to the c-axis. Micropipes are characteristic defects to the c-axis growth, while a large number of stacking faults are introduced during growth perpendicular to the c-axis. We discuss the cause and mechanism of the defect formation

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vectors > 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = lc with no hollow core) in densities on the order of thousands per cm 2, nearly 100-fold micropipe densities. While not nearly as detrimental to SiC device performance as micropipes, it has been previously shown that diodes containing elementary screw dislocations exhibit a 5% to 35% reduction in breakdown voltage, higher pre-breakdown reverse leakage current, softer reverse breakdown I-V knee, and concentrated microplasmic breakdown current filaments when measured under DC testing conditions. This paper details the impact of elementary screw dislocations on the experimentally observed reverse-breakdown pulse-failure characteristics of low-voltage (< 250 V) small-area (< 5 × 10-4 cm2) 4H-SiC p+n diodes. The presence of elementary screw dislocations did not significantly affect the failure properties of these diodes when subjected to non-adiabatic breakdown-bias pulsewidths ranging from 0.1 μs to 20 μs in duration. Diodes with and without elementary screw dislocations exhibited positive temperature coefficient of breakdown voltage and high junction failure power densities well above the failure power densities exhibited by highly reliable silicon power rectifiers. This preliminary result, based on measurements from one wafer of SiC diodes, suggests that highly reliable low-voltage SiC rectifiers may be attainable despite the presence of elementary screw dislocations.

The production of large diameter, high quality boules of SiC is essential to realize the full potential of this important semiconductor material. The objective of this paper is to provide a state-of-the-art analysis of the key directions for SiC bulk growth research, as well as presenting our most recent empirical results. Based on an analytical review of current knowledge, the following topics concerning growth of large 6H and 4H-SiC bulk crystals are discussed: 1) thermodynamics of the vapor phase including the efficiency of crystal growth, 2) kinetics of growth including mass transport in the boundary layer and 3) defect formation processes including thermoelastic stress. In addition, results of growth modeling are summarized and direction for further work suggested. Results on growth of semi-insulating and 50–75 mm diameter 4H-SiC wafers are presented. A discussion on micropipes, which are currently the most harmful defect in SiC wafers is presented. Although several mechanisms, or combinations of mechanisms, cause micropipes in SiC boules grown by the seeded sublimation method, we have reduced micropipe densities by orders of magnitude over the last few years. This continual reduction and the production of wafers with micropipe densities of less than 1 cm-2 (with >1 cm2 areas void of micropipes), indicate that micropipes will be reduced to a level that makes high current devices viable and that they may soon be totally eliminated.

The characteristics of SiC high-power devices are currently limited by the small area of the devices, which is usually less than 1 sq. mm. In order to increase device area, defect density in SiC epitaxial structures must be reduced. In this paper, we describe properties of silicon carbide epitaxial layers grown on 4H-SiC wafers with reduced micropipe density. These layers were grown by the vacuum sublimation method. Large area Schottky barriers (up to 8 mm2) were fabricated on SiC epitaxial layers and characterized.

The as-grown surfaces of 6H SiC seed crystals grown by the Lely method have been characterized by visible light microscopy and atomic force microscopy. The surfaces were then used to seed the sublimation growth of SiC at 2300°C, in 650 torr of Ar, with a gradient of 8 °C/cm. Repeated observations of the seed surface structure after predetermined intervals in the growth reactor demonstrated that transport starts at less than 2160 °C and that voids are nucleated by heterogeneous material on the original seed surface. Near these voids, the concentration of unit screw dislocations is increased and these defects migrate during growth. Screw dislocations of opposite sign act as step sources and build mesa structures around the heterogeneous material. After only 10 min at the growth temperature, micropipe/super screw dislocation complexes form in the centers of the mesas, possibly by the migration of unit dislocations to the voids.

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector > 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = Ic with no hollow core) in densities on the order of thousands per cm2, nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current-voltage (I-V) characteristics of 4H-SiC p+n diodes. First, Synchrotron White Beam X-ray Topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p+n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I-V knee, and no visible concentration of breakdown current. In contrast devices that contained at least one elementary screw dislocation exhibited a 5% to 35% reduction in breakdown voltage, a softer breakdown I-V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.

In this paper we demonstrate the growth of thick SiC epitaxial layers (≥100 μm) of good structural quality at a high growth rate (>100 μm/hr) by controlling the vapor dynamics during conventional physical vapor transport (PVT) process. We propose that our PVT technique be used to ‘repair’ or ‘heal’ commercially available substrates dominated by micropipes, by ‘filling up’ the micropipes through crystal growth inside the micropipe. Extensive experiments performed on thick SiC epitaxial layers grown on Lely substrates indicate that the thick epitaxial layers are of single polytype of high structural quality, with a single peak X-ray rocking curve of less than 12 arcsecs FWHM.

The growth surface of a 6H-SiC boule, grown by physical vapor transport, was examined using scanning force microscopy. The dimensions of surface/micropipe intersections and screw dislocation Burgers vectors have been determined from topographic data. All micropipes are positioned along the lines of super screw dislocations with a Burgers vectors of at least 4 times the c-axis repeat distance (15.2 Å). Perfect c-axis screw dislocations with Burgers vectors of only 15.2 Å are stable and do not have open cores. Measurements show that micropipe core radii, determined indirectly from the width of the craters formed at the surface/micropipe intersections, increase with the square of the dislocation Burgers vector.

A new technique for investigation of the electrical effects of micropipes in single-crystal 6H-SiC is presented. The setup allows the application of a parallel or normal electric field to MSM (metal-semiconductor-metal) test structures and the visualization of light emission sites in the test gap, including light activity underneath the metal contact. A special transparent metal [indium-tin-oxide(ITO)] was chosen for the metallic contacts. A map of micropipe locations was initially obtained at zero applied field using a laser scattering method. The initial map is compared with that of light emissions at different applied fields.Several tests on undoped and vanadium-doped (compensated) SiC, using NiCr/Au or ITO contacts, indicated the rapid activation of micropipes at relatively low fields in vertical MSM devices. A good match between the laser imaging map of micropipes at zero field and the map of field-induced light emission sites indicates that micropipes are the main current paths in vertical devices, carrying a large current density, and leading to light emissions and partial or total bulk breakdown of the test device.

Micropipes, the hollow cores of superscrew dislocations that lie along the c-direction in SiC single crystals, are quite deleterious to the performance of semiconductor devices. In the x-ray topography of longitudinal-cut samples of these crystals, topographs in the reflection (006) show dislocation image contrast associated with the superscrew dislocations lying along the c-axis of the crystal, which is also the direction of the dislocations' Burgers vectors. In the (110) reflection, whose g-vector is perpendicular to the c-axis and the dislocations' Burgers vector, there is also an image of the superscrew dislocation formed, albeit weaker than the corresponding image in the (006) reflection. This dislocation image is thought to represent stress components of the superscrew dislocation in directions perpendicular to the c-axis.In order to investigate the origin of these stress components, steps have been carried out to determine whether the dislocation image is anisotropic in all possible reflections where g={110}. To achieve this we have excised a hexagonal prism-shaped sample from a 6H-SiC wafer, 100μm wide, polished along the six {100} crystallographic faces, such that a single micropipe ran along the axis of the sample. This enabled x-ray topographs to be taken through each of these {100} faces

Stacking faults in a perfect crystal can be seen as limiting structures of certain series of polytypes of that crystal. A parametrization of the energy of polytypes in terms of interaction constants between layers therefore allows for the calculation of stacking-fault energies. The first-principles pseudopotential-density-functional method is used to calculate total energies of a few simple polytypes of silicon and carbon. The energies of intrinsic and extrinsic stacking faults (γISF and γESF , respectively) in silicon and diamond that follow from these calculations are in much better agreement with available experimental numbers than in previous theoretical approaches. I find: γISF = 47 mJm-2 and γESF = 36 mJm-2 for Si, γISF = 300 mJm-2 and γESF = 253 mJm-2 for diamond. From recently published similar calculations for polytypes of silicon carbide one obtains a negative energy for the extrinsic stacking fault, if zincblende silicon carbide is taken as the unfaulted structure, suggesting the observed occurrence in nature of polytypism in silicon carbide.

Ions of aluminum, gallium and nitrogen were implanted into (100) oriented β-SiC thin films at temperatures of 623K, 823K and 1023K. Rutherford backscattering/ion channeling analyses revealed that implantation of any one of the ionic species at 623K resulted in only slight crystal lattice damage. In comparison, implantation conducted using the same dosimetry and energy at room temperature resulted in extensive lattice damage; in the case of gallium, amorphization occurred. The backscattered yield from samples implanted at 1023K was nearly that of a virgin aligned spectra. This in situ annealing effect did not, however, result in the complete electrical activation of implanted species. In order to increase the percent of electrical activation, samples were annealed at 1473K for 1800s following implantation. Differential capacitance-voltage, spreading resistance and sheet resistance measurements were made in order to electrically characterize these layers. These measurements indicated the activation of p-type and n-type species in samples implanted with aluminum or gallium and nitrogen, respectively. The authors have previously reported p-type formation in β-SiC implanted with aluminum at room temperature following a 2073K - 300s anneal. By heating to 1023K during implantation and annealing at 1473K after implantation, improved structural and electrical properties have been achieved.