Search

Abstract Previous task mapping assumes that applications directly fetch data on remote nodes and build up their energy efficient mapping based on pattern of the NoC traffic. However, the data movement is actually managed by a cache coherence mechanism that executes a much more complicated protocol under application layer to guarantee data correction. Thus, we propose an energy efficient task mapping referring the protocol layer, rather than application layer, to precisely model protocol activities and energy dissipation. By a probabilistic description of cache accessing, we find a efficient method to convert application activities to energy consumption, generating an energy evaluation as a global optimization goal. We also propose a task mapping algorithm to minimize the energy consumption by referring activity intensity of the protocol. The experimental results show that the proposed energy model achieves a precision with less than 2% error and provides a credible quantitative criterion for energy optimization of cache coherence protocols. Comparing to application-layer optimization, our task mapping can obtain 20% energy saving and 15% latency reduction on average. [ABSTRACT FROM AUTHOR]

Employing adaptable protocol processing architectures has shown a high potential in provisioning Quality-of-Service (QoS) while retaining efficient use of available energy budget. Nevertheless, successful QoS provisioning using adaptable protocol processing architectures requires adaption to be agile and to have low latency. That is, a long adaptation latency might lead to violating desired packet processing latency, desired throughput or loss of packets if the memory fails to accommodate packet accumulation. This paper presents an elastic management scheme to permit agile and QoS-aware adaptation of processing elements (PEs) within the protocol processing architecture, such that desired QoS is maintained. Moreover, our proposed scheme has the potential to reduce energy consumption since it employs the PEs upon demand. We quantify the latency required for PEs adaptation, the reduction in energy and the reduction in area that can be achieved using our scheme. We also consider two different real-life use cases to demonstrate the effectiveness of our proposed management scheme in maintaining QoS while conserving available energy. [ABSTRACT FROM AUTHOR]

The last level cache (LLC) in private configurations offer lower latency and isolation but extinguishes the possibility of sharing underutilized cache resources. Cooperative Caching (CC) provides capacity sharing by spilling a line evicted from one cache to another. However, CC proposals did not pay enough attention to the natural problem of private LLC, replication. The static policies either indulging the replicated blocks (replicas) in or excluding them out of LLC invariably are deficient for the complex cache capacity situations in manycore environment. In this paper, we present replication-aware cache management (RACMan) to optimize replication for private configurations. RACMan relies on a novel coarse-grained low-overheard mechanism PBFP that monitors and predicts the replica reusability to dynamically adjust LLC insertion policies giving replicas different positions of LRU chain and chances of survival in LLC according to the prediction. Experiment results show our proposal is competent to optimize replication by performing better than two baseline systems in the respects of L2 Hit Rate, Network Traffics, IPC, and Dynamic Energy. RACMan fulfils the requirements of manycore CMPs with private LLC for increasing system performance, area efficiency, and scalability. [ABSTRACT FROM AUTHOR]

Aggressive scaling of the CMOS process technology allows the fabrication of highly integrated chips, and enables the design of the network-on-chip (NoC). However, it also leads to widespread reliability problems. A reliable NoC system must operate normally even in the face of a lot of transistor failures. Aiming towards permanent faults on communication links, we introduce a fault-tolerant MPI-like communication protocol. It detects the link failure if there exist unresponsive requests and automatically starts the new path exploration. The region flooding algorithm is proposed to search for a fault-free path and reroute packets to avoid system stalls. The experimental result shows our approach significantly reduces the latency compared with the basic flooding algorithm. The maximum latency reduction is 25% under the bit complement traffic pattern. Also, it brings only 2% fault tolerance loss. [ABSTRACT FROM AUTHOR]

In some scenarios, the cryptographic primitives should support more than one functionality. Authenticated Encryption/Verified Decryption (AEVD) combines encryption and authentication at the same time, which is useful in communication protocols (DNS, IPSEC, etc.). Nevertheless, authenticated encryption needs some optimizations to ensure fast performance. One solution could be the use of the Galois Counter Mode (GCM) scheme. To reach fast performances, this work broadens some GCM models described in Chakraborty et al.’s [D. Chakraborty, C. Mancillas Lopez, F. Rodriguez Henriquez, P. Sarkar, Efficient hardware implementations of BRW polynomials and tweakable enciphering schemes, Comput IEEE Trans 62 (2) (2013) 279–294, doi:10.1109/TC.2011.227] work with two changes. The first one is focused on speeding-up the polynomial multiplier necessary to perform the authentication process. That polynomial multiplier is extended for supporting four stages, based on the well-known Karatsuba–Ofman algorithm. The second one is the modification of two known block ciphers such as Camellia-128 and SMS4 with the GCM scheme. The constructed GCM is able to support variable-length messages greater than 512 bits. The throughput of the polynomial multiplier is greater than 28 Gbps for all the tested platforms. The independent block ciphers in encryption-only mode reach a throughput greater than 28 Gbps, and for all the GCM cases reported in this manuscript the throughput is greater than 9.5 Gbps. [ABSTRACT FROM AUTHOR]

In the era of Industry 4.0, the industrial internet of things (IIoT) is expected to transform traditional manufacturing. Machine vision, as the key enabling technology, can reduce maintenance and costs and improve production efficiency. This paper proposes an innovative machine vision system that uses the Gigabit Modbus user datagram protocol fieldbus. The protocol uses hardware and cross-layer function controllers to achieve edge computing with real-time image transmission. Results demonstrated that our innovative high-performance industrial machine vision solution can meet the requirements of IIoT applications. Moreover, the system considerably reduces the real-time response time and has superior usability compared with existing Ethernet fieldbus solutions. [ABSTRACT FROM AUTHOR]

In this paper, a comprehensive study is first conducted to investigate the effects of cache coherence protocols and cache replacement policies on the characteristics of NUCA in current many-core processors. The main focus of this study is to analyze the effects of coherence protocols and replacement policies on the vulnerability of caches. The outcomes of this analysis indicate two facts: (i) Differences in handling write operations play an important role to make distinction in favor of or against a cache coherence protocol; (ii) Near-optimal solutions for replacement problem, aimed at enhancing the performance, can also make positive influence on reduction of cache vulnerability factor. Based on the results of first step, two schemes are introduced to enhance the reliability of caches by applying some modification on the structures of cache coherence protocols and cache replacement policies. The first scheme tries to manage sharing of the dirty data items among different same-level caches. The second helps to give priority and more opportunity to old dirty blocks than clean blocks for replacement. The proposed schemes reveal about 18% improvement in MTTF, with negligible performance, bandwidth and energy consumption overhead compared to previous cache structures. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, the hardware implementations of six representative stream ciphers are compared in terms of performance, consumed area and the throughput-to-area ratio. The stream ciphers used for the comparison are ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. ZUC, Snow3g and E0 have been used for the security part of well known standards, especially wireless communication protocols. In addition, Grain V1, Mickey V2 and Trivium are currently selected as the final portfolio of stream ciphers for Profile 2 (Hardware) by the eStream project. The designs were implemented by using VHDL language and for the hardware implementations a FPGA device was used. The highest throughput has been achieved by Snow3g with 3330Mbps at 104MHz and the lowest throughput has been achieved by E0 with 187Mbps at 187MHz. Also, the most efficient cipher for hardware implementation in terms of throughput-to-area ratio is Mickey V2 cipher while the worst cipher for hardware implementation is Grain V1. [Copyright &y& Elsevier]

Abstract: Coherence protocols consume an important fraction of power to determine which coherence action to perform. Specifically, on CMPs with shared cache and directory-based coherence protocol implemented as a duplicate of local caches tags, we have observed that a big fraction of directory lookups cause a miss, because the block looked up is not allocated in any local cache. To reduce the number of directory lookups and therefore the power consumption, we propose to add a filter before the directory access. We introduce two filter implementations. In the first one, filtering information is explicitly kept in the shared cache for every block. In the second one, filtering information is decoupled from the shared cache organization, so the filter size does not depend on the shared cache size. We evaluate our filters in a CMP with 8 in-order processors with 4 threads each and a memory hierarchy with write-through local caches and a shared cache. We show that, for SPLASH2 benchmarks, the proposed filters reduce the number of directory lookups performed by 60% while power consumption is reduced by ∼28%. For Specweb2005, the number of directory lookups performed is reduced by 68% (44%), while directory power consumption is reduced by 19% (9%) using the first (second) filter implementation. [Copyright &y& Elsevier]

Abstract: The content addressable memory (CAM) based solutions are very useful in network applications due to its high speed parallel search mechanism. This paper presents a novel Ternary CAM (TCAM) based NAND Pseudo CMOS–Longest Prefix Match (NPC–LPM) search engine. The proposed system provides a simple hardware based solution using novel 11T TCAM cell structures and NPC word line technique, for network routers. The experiments were performed on 256×128 NPC–LPM system under 0.13μm technology. The simulation result shows that the proposed design provides low power dissipation of 5.78mW and high search speed of 315MSearches/s under 1.3V supply voltage. The presented NPC–LPM system meets the speed requirement of Optical Carrier (OC) 3072 with line-rate of 160Gb/s in Ethernet networking and IPv6 protocol. The experimental results also show that the proposed system improves power-performance by 65%. [Copyright &y& Elsevier]

Abstract: The input buffers of the current packet-switched Network-on-Chip (NoC) architectures consume a significant portion of the total power of the interconnection network. Reducing the size of input buffers would result in degraded performance, while eliminating all buffers would result in increased power at high network load. In this article, we propose DXbar: an innovative dual-crossbar design. By combining the advantages of buffered and bufferless networks, we achieve at least 20% performance improvement in terms of throughput and latency, and at least 20% power saving over buffered networks with virtual channels. Furthermore, DXbar can outperform current bufferless networks with deflecting and dropping protocols while consuming at most half of the power. [Copyright &y& Elsevier]

Abstract: This paper presents the design and implementation of a protocol offload engine that processes TCP/IP and remote direct memory access (RDMA) protocols by means of hardware/software coprocessing. In the offload engine, time-consuming operations such as TCP/IP header generation are implemented as hardware to improve performance. The software performs control operations and RDMA header generation. In the experiments and analyses, it is proved that the hardware can provide satisfactory performance to process all operations at speeds of over 1Gbps. Our engine can offload most protocol processing overheads – up to 95% to 100% – from the host CPU. Finally, although the embedded processors operate with a 300MHz clock that is seven times slower than the clock of the host CPU, our engine shows maximum bandwidths of 673Mbps for TCP/IP and 551Mbps for RDMA on a gigabit Ethernet network. [Copyright &y& Elsevier]

To devise effective network engineering strategies and to assess the quality of upstream providers, network operators would greatly benefit from the knowledge of which Internet paths might be traversed by the traffic flows entering their networks in the case of network faults or when traffic engineering measures are used. However, current methodologies do not provide this information. This paper presents methodologies to discover alternate paths that might be selected in the presence of network faults or different routing policies and to deduce the routing policies of other operators. The techniques are validated through extensive experimentation on the Internet. [Copyright &y& Elsevier]

In this paper, we present a Programmable Packet Processing Engine suitable for deep header processing in high-speed networking systems. The engine, which has been – fabricated as part of a complete network processor, consists of a typical RISC-CPU, whose register file has been modified in order to support efficient context switching, and two simple special-purpose processing units. The engine can be used in a number of network processing units (NPUs), as an alternative to the typical design practice of employing a large number of simple general purpose processors, or in any other embedded system designed to process mainly network protocols. To assess the performance of the engine, we have profiled typical networking applications and a series of experiments were carried out. Further, we have compared the performance of our processing engine to that of two widely used NPUs and show that our proposed packet-processing engine can run specific applications up to three times faster. Moreover, the engine is simpler to be fabricated, less complex in terms of hardware complexity, while it can still be very easily programmed. [Copyright &y& Elsevier]

The automotive industry is now incorporating ‘control-by-wire’ features into vehicles, to control the most safety-critical systems such as braking and steering. Such systems are referred to as ‘X-by-wire’ systems, where X refers to the specific type of system that is being controlled. The requirements for the multiplexed control network in X-by-wire systems demand the use of fast, safe, fault-tolerant, in-vehicle control networks. Research has established the time-triggered architecture as the most suitable approach for X-by-wire applications. In the time-triggered architecture, all activity of message exchange is synchronized to a global timebase and all nodes in the network perform their tasks based on a message schedule, which is strictly synchronized to this global timebase. A number of different types of control network protocols are emerging, based on the time-triggered architecture. The industry will soon decide on which of these networks will become the de-facto standards for X-by-wire applications. Other future network protocols will also find use in the automotive systems and there will be a need to communicate control message data across different types of time-triggered networks, with different specifications and protocols; realizing the need for a new type of real-time gateway for time-triggered control networks. Such a gateway concept is proposed in this paper and its design architecture is described at an early prototype level. A FPGA based digital IC is developed to demonstrate the concept. The prototype has been evaluated and the results are presented to show the deterministic real-time behaviour of the gateway. Four types of state-of-the-art time-triggered networks are supported in the prototype design, i.e., FlexRay, Byteflight, TTP/C and TTCAN. The core gateway architecture has been adopted from state-of-the-art packet switching techniques as used in ATM networks. Special purpose Network Host Processors (NHP) implement the protocol conversion routines to convert frames from network to gateway core format and vice versa. [Copyright &y& Elsevier]

We analyze the computation overhead of the IP security protocol (IPSec) on a handheld device. We design experiments to quantify the energy consumed by the individual components in IPSec. We then experiment with several measures which can potentially cut the energy consumption without compromising security. Our results show that by replacing 3DES with Advanced Encryption Standard as the encryption algorithm, the total energy consumption is reduced by up to 38%. On the other hand, MD5 and SHA-1 consume about the same amount of energy for message authentication, which makes SHA-1 more preferred because of its known higher strength against birthday attacks. We also find that the power-saving mode of the wireless LAN interface does not reduce (and may even increase) the total energy cost despite the substantial amount of network idle time. Finally, we find that the data compression option must be used carefully. When sending data from the handheld device, the lossless compression used in IPSec can actually increase the energy consumption until the network bandwidth drops down to 2Mbps or lower. However, compression is found to save energy when the device receives compressible data under normal bandwidths. This result suggests that the compression option must be dynamically changed in IPSec between data transmission and reception. [Copyright &y& Elsevier]

The task of an Internet router is to scan the IP headers for the destination address and make a routing decision based on the information. If the processing capability of a router is enhanced to support computation on a datagram, some of the host computation may be delegated to the intermediate routers. The instructions about how to do the processing may be provided by the end hosts. We propose a reliable transport layer protocol, Intermediate Processing Protocol (IPP) for processing within the Internet. The protocol design makes provisions for connection set up handshake, router reservation, intermediate processing, data acknowledgement, buffering and retransmission, flow and congestion control, ordered delivery and security issues. [Copyright &y& Elsevier]

In this paper, a reconfigurable memory architecture and lookup technique for IP packet forwarding engines is presented. This is achieved by partitioning the forwarding table into smaller partial lookup tables for each output port and allowing a forwarding engine to process them in parallel. This effectively reduces the complexity of finding the ‘longest prefix match’ problem to the ‘first prefix match’ problem. Our method is a flexible technique that significantly elevates the scalability of the next generation network processors and other packet processing devices. Such scalability facilitates migration to IPv6 and benefits network equipments especially in terms of growing routing table size, traffic, frequency of route updates and bandwidth requirement. [Copyright &y& Elsevier]

Wireless technology allows one or more devices to communicate without the need for a physical connection. Wireless technology and wired technology applications use a wireless frequency transmission device for transmitting data while using a cable. In the case of wireless medical data transmission, it can cover a large area of the home and domestic users. This guide evaluates and compares, and defines specific application scenarios for Wireless Personal Area Networks (WPAN), Wireless Local Area Networks (WLAN), and Wireless Metropolitan Area Networks (WAN) operating in a moderate computer field. The extraction of standard terms in the computer field provides a measurement and control network protocol for the home and residential communities that enables them to achieve green and smarter features. It specifies the data format of the interaction between the device and the system and provides a standardized definition of sensors, actuators, and devices, along with data communication processing. This standard includes method definition test configuration and management capabilities, deployment and orientation control-related features, conformance testing, and data format definitions for interoperability. Independent protocol is defined for discovering and establishing media access methods. This standard supports between ports connected to the same access network, including intercommunication between ports and ports General support specified in secure communication Architectural, functional elements, and protocols. Authentication with IEEE 802.1AE ™ MAC (Mobile Access Control) uses security associations securely. [ABSTRACT FROM AUTHOR]

Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5. [ABSTRACT FROM AUTHOR]