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Abstract: In this paper, the hardware implementations of six representative stream ciphers are compared in terms of performance, consumed area and the throughput-to-area ratio. The stream ciphers used for the comparison are ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. ZUC, Snow3g and E0 have been used for the security part of well known standards, especially wireless communication protocols. In addition, Grain V1, Mickey V2 and Trivium are currently selected as the final portfolio of stream ciphers for Profile 2 (Hardware) by the eStream project. The designs were implemented by using VHDL language and for the hardware implementations a FPGA device was used. The highest throughput has been achieved by Snow3g with 3330Mbps at 104MHz and the lowest throughput has been achieved by E0 with 187Mbps at 187MHz. Also, the most efficient cipher for hardware implementation in terms of throughput-to-area ratio is Mickey V2 cipher while the worst cipher for hardware implementation is Grain V1. [Copyright &y& Elsevier]

The automotive industry is now incorporating ‘control-by-wire’ features into vehicles, to control the most safety-critical systems such as braking and steering. Such systems are referred to as ‘X-by-wire’ systems, where X refers to the specific type of system that is being controlled. The requirements for the multiplexed control network in X-by-wire systems demand the use of fast, safe, fault-tolerant, in-vehicle control networks. Research has established the time-triggered architecture as the most suitable approach for X-by-wire applications. In the time-triggered architecture, all activity of message exchange is synchronized to a global timebase and all nodes in the network perform their tasks based on a message schedule, which is strictly synchronized to this global timebase. A number of different types of control network protocols are emerging, based on the time-triggered architecture. The industry will soon decide on which of these networks will become the de-facto standards for X-by-wire applications. Other future network protocols will also find use in the automotive systems and there will be a need to communicate control message data across different types of time-triggered networks, with different specifications and protocols; realizing the need for a new type of real-time gateway for time-triggered control networks. Such a gateway concept is proposed in this paper and its design architecture is described at an early prototype level. A FPGA based digital IC is developed to demonstrate the concept. The prototype has been evaluated and the results are presented to show the deterministic real-time behaviour of the gateway. Four types of state-of-the-art time-triggered networks are supported in the prototype design, i.e., FlexRay, Byteflight, TTP/C and TTCAN. The core gateway architecture has been adopted from state-of-the-art packet switching techniques as used in ATM networks. Special purpose Network Host Processors (NHP) implement the protocol conversion routines to convert frames from network to gateway core format and vice versa. [Copyright &y& Elsevier]