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Abstract Previous task mapping assumes that applications directly fetch data on remote nodes and build up their energy efficient mapping based on pattern of the NoC traffic. However, the data movement is actually managed by a cache coherence mechanism that executes a much more complicated protocol under application layer to guarantee data correction. Thus, we propose an energy efficient task mapping referring the protocol layer, rather than application layer, to precisely model protocol activities and energy dissipation. By a probabilistic description of cache accessing, we find a efficient method to convert application activities to energy consumption, generating an energy evaluation as a global optimization goal. We also propose a task mapping algorithm to minimize the energy consumption by referring activity intensity of the protocol. The experimental results show that the proposed energy model achieves a precision with less than 2% error and provides a credible quantitative criterion for energy optimization of cache coherence protocols. Comparing to application-layer optimization, our task mapping can obtain 20% energy saving and 15% latency reduction on average. [ABSTRACT FROM AUTHOR]

Employing adaptable protocol processing architectures has shown a high potential in provisioning Quality-of-Service (QoS) while retaining efficient use of available energy budget. Nevertheless, successful QoS provisioning using adaptable protocol processing architectures requires adaption to be agile and to have low latency. That is, a long adaptation latency might lead to violating desired packet processing latency, desired throughput or loss of packets if the memory fails to accommodate packet accumulation. This paper presents an elastic management scheme to permit agile and QoS-aware adaptation of processing elements (PEs) within the protocol processing architecture, such that desired QoS is maintained. Moreover, our proposed scheme has the potential to reduce energy consumption since it employs the PEs upon demand. We quantify the latency required for PEs adaptation, the reduction in energy and the reduction in area that can be achieved using our scheme. We also consider two different real-life use cases to demonstrate the effectiveness of our proposed management scheme in maintaining QoS while conserving available energy. [ABSTRACT FROM AUTHOR]

The last level cache (LLC) in private configurations offer lower latency and isolation but extinguishes the possibility of sharing underutilized cache resources. Cooperative Caching (CC) provides capacity sharing by spilling a line evicted from one cache to another. However, CC proposals did not pay enough attention to the natural problem of private LLC, replication. The static policies either indulging the replicated blocks (replicas) in or excluding them out of LLC invariably are deficient for the complex cache capacity situations in manycore environment. In this paper, we present replication-aware cache management (RACMan) to optimize replication for private configurations. RACMan relies on a novel coarse-grained low-overheard mechanism PBFP that monitors and predicts the replica reusability to dynamically adjust LLC insertion policies giving replicas different positions of LRU chain and chances of survival in LLC according to the prediction. Experiment results show our proposal is competent to optimize replication by performing better than two baseline systems in the respects of L2 Hit Rate, Network Traffics, IPC, and Dynamic Energy. RACMan fulfils the requirements of manycore CMPs with private LLC for increasing system performance, area efficiency, and scalability. [ABSTRACT FROM AUTHOR]

Aggressive scaling of the CMOS process technology allows the fabrication of highly integrated chips, and enables the design of the network-on-chip (NoC). However, it also leads to widespread reliability problems. A reliable NoC system must operate normally even in the face of a lot of transistor failures. Aiming towards permanent faults on communication links, we introduce a fault-tolerant MPI-like communication protocol. It detects the link failure if there exist unresponsive requests and automatically starts the new path exploration. The region flooding algorithm is proposed to search for a fault-free path and reroute packets to avoid system stalls. The experimental result shows our approach significantly reduces the latency compared with the basic flooding algorithm. The maximum latency reduction is 25% under the bit complement traffic pattern. Also, it brings only 2% fault tolerance loss. [ABSTRACT FROM AUTHOR]

In some scenarios, the cryptographic primitives should support more than one functionality. Authenticated Encryption/Verified Decryption (AEVD) combines encryption and authentication at the same time, which is useful in communication protocols (DNS, IPSEC, etc.). Nevertheless, authenticated encryption needs some optimizations to ensure fast performance. One solution could be the use of the Galois Counter Mode (GCM) scheme. To reach fast performances, this work broadens some GCM models described in Chakraborty et al.’s [D. Chakraborty, C. Mancillas Lopez, F. Rodriguez Henriquez, P. Sarkar, Efficient hardware implementations of BRW polynomials and tweakable enciphering schemes, Comput IEEE Trans 62 (2) (2013) 279–294, doi:10.1109/TC.2011.227] work with two changes. The first one is focused on speeding-up the polynomial multiplier necessary to perform the authentication process. That polynomial multiplier is extended for supporting four stages, based on the well-known Karatsuba–Ofman algorithm. The second one is the modification of two known block ciphers such as Camellia-128 and SMS4 with the GCM scheme. The constructed GCM is able to support variable-length messages greater than 512 bits. The throughput of the polynomial multiplier is greater than 28 Gbps for all the tested platforms. The independent block ciphers in encryption-only mode reach a throughput greater than 28 Gbps, and for all the GCM cases reported in this manuscript the throughput is greater than 9.5 Gbps. [ABSTRACT FROM AUTHOR]

In the era of Industry 4.0, the industrial internet of things (IIoT) is expected to transform traditional manufacturing. Machine vision, as the key enabling technology, can reduce maintenance and costs and improve production efficiency. This paper proposes an innovative machine vision system that uses the Gigabit Modbus user datagram protocol fieldbus. The protocol uses hardware and cross-layer function controllers to achieve edge computing with real-time image transmission. Results demonstrated that our innovative high-performance industrial machine vision solution can meet the requirements of IIoT applications. Moreover, the system considerably reduces the real-time response time and has superior usability compared with existing Ethernet fieldbus solutions. [ABSTRACT FROM AUTHOR]

In this paper, a comprehensive study is first conducted to investigate the effects of cache coherence protocols and cache replacement policies on the characteristics of NUCA in current many-core processors. The main focus of this study is to analyze the effects of coherence protocols and replacement policies on the vulnerability of caches. The outcomes of this analysis indicate two facts: (i) Differences in handling write operations play an important role to make distinction in favor of or against a cache coherence protocol; (ii) Near-optimal solutions for replacement problem, aimed at enhancing the performance, can also make positive influence on reduction of cache vulnerability factor. Based on the results of first step, two schemes are introduced to enhance the reliability of caches by applying some modification on the structures of cache coherence protocols and cache replacement policies. The first scheme tries to manage sharing of the dirty data items among different same-level caches. The second helps to give priority and more opportunity to old dirty blocks than clean blocks for replacement. The proposed schemes reveal about 18% improvement in MTTF, with negligible performance, bandwidth and energy consumption overhead compared to previous cache structures. [ABSTRACT FROM AUTHOR]

Wireless technology allows one or more devices to communicate without the need for a physical connection. Wireless technology and wired technology applications use a wireless frequency transmission device for transmitting data while using a cable. In the case of wireless medical data transmission, it can cover a large area of the home and domestic users. This guide evaluates and compares, and defines specific application scenarios for Wireless Personal Area Networks (WPAN), Wireless Local Area Networks (WLAN), and Wireless Metropolitan Area Networks (WAN) operating in a moderate computer field. The extraction of standard terms in the computer field provides a measurement and control network protocol for the home and residential communities that enables them to achieve green and smarter features. It specifies the data format of the interaction between the device and the system and provides a standardized definition of sensors, actuators, and devices, along with data communication processing. This standard includes method definition test configuration and management capabilities, deployment and orientation control-related features, conformance testing, and data format definitions for interoperability. Independent protocol is defined for discovering and establishing media access methods. This standard supports between ports connected to the same access network, including intercommunication between ports and ports General support specified in secure communication Architectural, functional elements, and protocols. Authentication with IEEE 802.1AE ™ MAC (Mobile Access Control) uses security associations securely. [ABSTRACT FROM AUTHOR]

Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5. [ABSTRACT FROM AUTHOR]