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During technology development, the study of low- k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low- k TDDB are closely correlated with the leakage conduction mechanism of low- k dielectrics. In addition, low- k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low- k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low- k breakdown model. Then we review several other low- k TDDB models that consider only intrinsic low- k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low- k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low- k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low- k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.

The recovery mechanism observed in oxynitride gate pMOSFETs after negative bias temperature (NBT) stresses is reviewed. The recovery can be divided into two elements, fast recoverable- and permanent components (R and P). An interesting features, universality, observed in R was examined. In addition, the validity of the empirical equation previously proposed for the universality was confirmed from the perspective of the recovery activation energy distribution or R. Moreover, the origin of the defects responsible for recovery were investigated. R can be due to the annihilation of E ′ -centers (X3 Si++ Si O3, where denotes a dangling bond and X is oxygen or nitrogen). During a recovery period, the trapped holes are emitted from E ′ -centers, resulting in R. The hole emission begins immediately after NBT stresses because the emission energy is shallow. Therefore, the fast recovery, i.e., R is observed. On the other hand, several defects, interface states ( D it ) , fixed positive charges ( D pc ) , K-centers (N3 Si ) and E ′ -centers were involved in P. When NBT stresses were light, only D it and D pc were observed. The experimental data support a model where hydrogen emitted from interfacial Si H bonds by NBT the stresses reacts with adjacent Si X Si network in the SiON gate insulator, which leaves silicon dangling bonds (Si3 Si called P b -centers), i.e., D it , and forms the generation of Si X+H Si (overcoordinated oxygen or nitrogen, i.e., D pc ). Heavy NBT stresses generated additional defects, K- and E ′ -centers, which also act as D it and D pc . Moreover, these K- and E ′ -centers that were formed through the breaking of Si X bonds caused stress induced leakage current. Because the annihilation of P-related defects, D it , D pc , K-center and E ′ -center, requires very high temperature, P behaves as the permanent component under conventional NBT experimental temperature conditions. We reviewed these results and a model for the generation and recovery behaviors of defects.

This paper discusses time-dependent dielectric breakdown (TDDB) in n-FETs with HfSiON gate stacks under various stress conditions. It was found that the slope of Weibull distribution of Tbd, Weibull β, changes with stress conditions, namely, DC stress, unipolar AC stress and bipolar AC stresses. On the other hand, the time evolution component of stress-induced leakage current (SILC) was not changed by these stresses. These experimental results indicate that the modulation of electron trapping/de-trapping and hole trapping/de-trapping by stress condition changes the defect size in high-k gate dielectrics. Therefore, the control of injected carrier and the characteristics of trapping can provide the steep Weibull distribution of Tbd, leading to long-term reliability in scaled CMOS devices with high-k gate stacks.

Aim of this work is to give a complete overview of Flash memory cell reliability issues. The main physical mechanisms occurring during operating conditions are reviewed for understanding the technological limits of these memories. In particular, stress induced leakage current causes problems of single bit charge loss at room and at high temperature after cycling, while charge trapping and de-trapping degrade performance and operative memory window. Also random telegraph noise degrades memory window and process optimization has to be considered. The investigation of the physical mechanisms behind allows improving memory reliability giving suggestion for tunnel oxide quality optimization. In particular, tunnel oxide nitridation will be deeply investigated.

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO2 gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (Vt) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.

The electrical characteristics of HfO2–Ta2O5 mixed stacks under constant current stress (CCS) at gate injection with 20 mA/cm2 and stressing times of 50 and 200 s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes – positive charge build-up and new bulk traps generation – are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO2 layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta2O5–HfO2-based capacitors.

In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8 nm thick SiO 2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures.

In the present work we study reliability issues of Pt/HfO 2 /Dy 2 O 3 /n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge ( Q inj ) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.

Response of 8 nm Ta 2 O 5 stacks with Al and Au gate electrodes to voltage stress at room temperature and at 100 °C is investigated. Stress-induced leakage current (SILC) reveals significant gate dependence and distinct difference to SILC in SiO 2 . The mechanisms for SILC generation and stress degradation are discussed. Unlike SiO 2 , pre-existing traps and positive charge build-up are recognized as a key factor for generation of SILC in Ta 2 O 5 stacks.

We review the advancements in the understanding of breakdown and trap generation that have been achieved using low voltage stress-induced leakage current as a probe of the interface states created during electrical stress of ultra thin SiO2 and SiON gate dielectrics. The technique separates the effects of bulk and interface states on the post-stress I–V characteristics; senses interface traps at both contact interfaces, identifies the regime where interface rather than bulk state generation is the rate limiting step for breakdown, is useful for determining the operative trap creation processes, and reveals the role of trap generation mechanism in driving which stress-induced defect controls breakdown.

Ultra thin high- k zirconium oxide (equivalent oxide thickness ∼1.57 nm) films have been deposited on strained-Si/relaxed-Si 0.8 Ge 0.2 heterolayers using zirconium tetra- tert -butoxide (ZTB) as an organometallic source at low temperature ( 2 gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Stress induced leakage current (SILC) through ZrO 2 is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of ZrO 2 layer. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of ∼10 −19 cm 2 as compared to ∼10 −16 cm 2 in SiO 2 has been observed. The trapping charge density, Q ot and charge centroid, X t are also empirically modeled. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating layer. Dielectric breakdown and reliability of the dielectric films have been studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t bd > 1500 s) is observed under high constant voltage stress.

The degradation of Ta2O5-based (10 nm) stacked capacitors with different top electrodes, (Al, W, Au) under constant current stress has been investigated. The variation of electrical characteristics after the stress is addressed to gate-induced defects rather than to poor-oxidation related defects. The main wearout parameter in Ta2O5 stacks is bulk-related and a generation only of bulk traps giving rise to oxide charge is observed. The post-stress current–voltage curves reveal that stress-induced leakage current (SILC) mode occurs in all capacitors and the characteristics of pre-existing traps define the stress response. The results are discussed in terms of simultaneous action of two competing processes: negative charge trapping in pre-existing electron traps and stress-induced positive charge generation, and the domination of one of them in dependence on both the stress level and the gate used. The charge build-up and the trapping/detrapping processes modify the dominant conduction mechanism and the gate-induced defects are precursors for device degradation. It is concluded that the impact of the metal gate on the ultimate reliability of high-k stacked capacitors should be strongly considered.

In this paper, reliability aspects of thin Zr- and Hf-silicate layers are addressed by analyzing the stress induced leakage current (SILC) and charge trapping during constant voltage stress (CVS) and constant current stress (CCS). Voltage polarity and temperature effects on the degradation of the layers are also studied. SILC in silicate layers is found to be strongly polarity dependent and it is suggested that the damage causing it is near silicate/Si interface. SILC has a transient component and its recovery is explained by the trapping/detrapping of traps participating in Poole–Frenkel conduction. Unlike SiO 2 , hot carrier induced damage is not the main mechanism for SILC creation. Therefore, the origin of SILC in silicate layers is distinctly different to SiO 2 .

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO2 tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.

Ultra-thin gate-oxide reliability is an essential factor in CMOS technologies. The low voltage gate current in ultra-thin oxide of metal–oxide–semiconductor devices is very sensitive to electrical stresses. It can be used as a reliability monitor when the oxide thickness becomes too small for traditional electrical measurements. In this paper, the low voltage stress induced leakage current (LVSILC) for various oxide thicknesses ranging from 1.2 to 2.3 nm is investigated during constant voltage stress (CVS). From the LVSILC measurements, we shown that time to breakdown can be deduced as a function of the stress voltage. We also study the effect of elevated stress temperature on the time to breakdown. We show that temperature dependence of the time to breakdown is non-Arrhenius and decreases in a drastic way with a slope of ∼0.036 decade/°C.

It is known that program/erase cycling of Flash memories induces a degradation of the tunnel oxide insulating property usually referred to as Stress-Induced Leakage Current (SILC). An issue related to SILC is the read disturb, affecting cells in an addressed word-line, which can cause electron injection through tunnel oxide in the floating gate of erased cells during read operation. Read disturb can also be present in Flash memory with a weak tunnel oxide quality: aim of this paper is to discuss in detail the effect of this read disturb phenomena. Cell Failure Density (CDF) extrapolation from experimental data using statistical method is able to estimate defect probability and application’s failure rate for both SILC and weak tunnel oxide quality cases.

A simplified quantitative model for the steady-state component of stress-induced leakage current (SILC) in MOS capacitors with ultrathin oxide layers has been developed by assuming a two-step inelastic trap-assisted tunneling (ITAT) process as the conduction mechanism. By using our model, we reduced the time of numerical calculations of SILC to 17% of the standard method while maintaining a high accuracy of the results. We also confirmed that the SILC component must not be neglected when calculating the gate current in modern devices, especially at low fields. Our simplified model helped us to investigate the dependence of SILC on the oxide field and the oxide thickness. We also shed some light on the reasons that cause the peak in the SILC–oxide thickness relation.

The carrier conduction and the degradation mechanism in n+gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlOX (Hf: 60 at.%, Al: 40 at.%)/SiO2 dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO2 layer (IL) thickness increases in a fixed high-k layer thickness (Thigh-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO2/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of Thigh-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n+poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n+poly-Si gate. Both the defect generation rate and the defect size in the HfAlOX/SiO2 stacks are large compared with those in SiO2. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO2 could be related to a larger dielectric constant of the high-k layer.

In this work we present two analytical (and physically supported) models to describe trap kinetics in both thin and ultra-thin SiO2 films. The models are based on the different mechanism controlling the carrier transport through the oxides and on the assumption of a two step process for creating stable traps, through defect precursors. Experimental data of stress induced leakage current confirm the validity of models predictions. Furthermore, a systematic study of the transient of trap kinetics experimentally demonstrates the existence of defect precursors as well as a reduction of oxide damage under pulsed stress condition respect to DC case.

International audience; The impact of hot electrons on gate oxide degradation is studied by investigating devices under constant voltage stress and substrate hot electron injection in thin silicon dioxide (2.5–1.5 nm). The build-up defects measured using low voltage stress induced leakage current is reported. Based on these results, we propose to extract the critical parameter of the degradation under simultaneous tunneling and substrate hot-electron stress. During a constant voltage stress the oxide field, the injected charge and the energy of carriers are imposed by VG and cannot be studied independently. Substrate hot electron injection allows controlling the current density independent of the substrate bias and oxide voltage. The results provide an understanding for describing the reliability and the parameters dependence under combined substrate hot electron injection and constant voltage stress tunneling.

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I g ( V g ), characteristics is thought to flow through Si–SiO 2 interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO 2 interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.

Experiments were performed on 2.3 nm thin gate oxides. The interface state density and the low voltage stress induced leakage current are compared after uniform and localized stresses. The energy distribution of interface state density in the bandgap is then determined. The normalized variations of interface state density and gate leakage current are shown to be comparable after localized stress but completely different after uniform stresses.

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell Vt in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.

IMOMEC, IMEC Div, B-3590 Diepenbeek, Belgium. IMEC, B-3001 Heverlee, Belgium. Limburgs Univ Ctr, Inst Mat Res, B-3590 Diepenbeek, Belgium.Aresu, S, IMOMEC, IMEC Div, Wetenschapspk 1, B-3590 Diepenbeek, Belgium.

IMOMEC, IMEC Div, B-3590 Diepenbeek, Belgium. Limburgs Univ Ctr, Mat Res Inst, B-3590 Diepenbeek, Belgium. IMEC, B-3001 Heverlee, Belgium.Aresu, S, IMOMEC, IMEC Div, Wetenschapspk 1, B-3590 Diepenbeek, Belgium.

In this study, body effect influence on oxide degradation is analyzed. It is found that the negative bias polarization on the n-well of a p-channel MOS transistor may induce a significant reduction of the oxide lifetime as well as an increase of stress-induced leakage current (SILC). Such a result is demonstrated to confirm the key role of hot holes on SILC and breakdown phenomena. Moreover, even if the hot hole generated at the anode are probably at the origin of SILC and can be interpreted as a catalyst of breakdown, it is undoubtedly shown that both phenomena are not directly correlated: SILC at breakdown can not be ascribed to a critical density of defect at failure.

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases. From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.

Extensive gate stress measurements after cycling on test structures and on products have been carried out on EEPROMS. The leakage current in the worst case SILC cell has been measured at very low electrical field (down to 1 MV/cm), and has been fitted with various formulae like Fowler-Nordheim (FN), Poole-Frenkel (PF), trap-assisted tunneling (TAT) and hopping conduction model (HCM). In such EEPROMS, a strong asymmetry of SILC has been found. The SILC at low-Vt state is worse than that at high-Vt state. The effect of pulse shaping on suppressing SILC is also demonstrated. A new method is reported to perform data retention estimation and product reliability based on field accelerated tests (gate stress tests). The data retention time of the SILC cell has been determined based on the worst case data from gate stress experiments. The new method can be applied to other floating gate non-volatile memories, such as flash.

International audience; We compare in this work, the electrical properties of gate leakage currents induced through the thin SiO2 oxide layer of metal-oxide-semiconductor structures by high energy ion implantation and high field stresses. Even if the high-frequency capacitance-voltage characteristics are very different after both treatments, a comparable increase and similar shapes are found at low fields in static gate current–voltage curves, typical of equivalent oxide damage. Moreover, these stress or implantation induced leakage currents (SILC or IILC, respectively) are both removed in a similar way by a thermal anneal under forming gas at 430°C. We conclude that similar defects could be induced through the oxide by both processes and generate those excess currents by a defect assisted tunneling mechanism.

The stress induced leakage current (SILC) in Si/SiO2 structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.

In this study, wet and dry oxidation processes for 3.5 nm ultrathin dielectrics are compared in terms of oxide and device reliability. It is demonstrated that a wet oxidation enables to strongly improve the oxide lifetime. On the contrary, the device reliability has been found to be slightly affected by the process choice. Finally, these results associated with charge pumping and stress induced leakage current measurements indicate that the bulk oxide, more than the Si/SiO2 interface, is affected by the growth process ambience (wet or dry oxidation).

Stress Induced Leakage Current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a veritable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime. The physical origin and mechanisms of SILC have not yet been clearly understood and several open points to discussion remain. In this work the electrical characteristics of SILC have been studied and an empirical reliability model for ultra-thin gate oxide has been proposed. Moreover, ionizing radiation effects in leakage current generation have been analyzed and compared to electrical SILC.

A thorough characterization of stress-induced leakage currents (SILCs) for a IOnm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.

A new model for the oxide thickness dependence of the SILC generation has been proposed on the basis of defects created by anode hole injection. This model which has been validated on oxides with thickness down to ≈3nm, allows the explanation of the bell-shaped behavior of the SILC variation with oxide thickness and predicts a strong reduction of the SILC intensity for ultra thin oxides operated in the direct tunneling regime.

The understanding of the transport mechanism at the origin of the leakage currents in thin oxides is crucial to make reliable data retention predictions. In this work we demonstrate that elastic resonant trap assisted tunnelling well describes the SILC (Stress Induced Leakage Current) for oxide thicknesses between 4 and 7.5 nm when an appropriate trap profile is used. Moreover our approach gives a qualitative description of the temperature dependence of the SILC, exhibiting similar field dependent activation energy. Finally we showed that the SILC measured in the substrate current could also be modeled using a trap assisted tunnelling model, demonstrating that this approach is consistent with the main experimental characteristics of the SILC.

Stress-induced leakage current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a reliable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime [1] . The physical origin and mechanisms of SILC have not yet been clearly understood and several points open to discussion remain. In this work the role of oxide hole fluence in producing the SILC is discussed. An universal power law of SILC generation kinetics is proposed versus the hole fluence throughout the oxide. The experimental results are theoretically validated by modeling the measured quantum-yield by the contributions of both anode hole injection and electron valence band injection mechanisms.

The annealing properties of the stress induced leakage current (SILC) for 55 and 65 Athick oxides are investigated. It is demonstrated that the SILC is a fully reversible degradation process and that its generation kinetics are nearly unchanged after successive stressing/annealing cycles. The activation energy and diffusion coefficient of the annealing process has been extracted and shown to be independent of oxide thickness. Moreover the annealing kinetics are quantitatively simulated using a drift-diffusion model with the experimentally extracted parameters.

This paper focuses on the stress-induced leakage current (SILC) phenomenon in 5 nm thin oxides. The statistical investigation of SILC is emphasized and it is shown that this phenomenon can be directly linked to the intrinsic properties of the SiO 2 material. Moreover, it will be pointed out that the experimentally validated SILC build-up empirical model presents some limitations when using this model for extrapolation purposes at very low injected charges and/or low current/voltage levels.

A new experimental method for the determination of the energy distribution of neutral traps in oxide is presented, based on an analysis of the transient SILC current. Results show that the stress damage is mostly located from about 2 to 2.7 eV from the oxide conduction band, and that a greater stress is generated at the anode side of the stress. Preliminary results of a detailed numerical model for the trap-assisted tunneling are presented, showing that an exponentially decaying trap profile within the oxide is needed to account for the discharge current transient.

Radiation-induced leakage current (RILC) has been studied on ultra-thin gate oxides (4 and 6 nm) irradiated with 8 MeV electrons. Both RILC and stress-induced leakage current (SILC) have been fitted with the same Fowler–Nordheim law, suggesting that RILC and SILC have similar conduction mechanisms. The RILC dependence from total dose during irradiation has been analysed and compared with the SILC dependence from the cumulative injected charge. Different growth laws of RILC and SILC have been found in the two cases. The intensity of positive and negative RILC also depends on the applied gate bias voltage during irradiation, probably reflecting different distributions of the oxide traps mediating the trap assisted tunnelling. Finally, we have presented the first evidence of a quasi-breakdown phenomenon due to ionizing radiation.

Stress-induced leakage current (SILC) has several components. One of these components increases when the oxide thickness decreases. We show that this component can be reduced by application of a low field of opposite polarity to the stress field or by temperature annealing. When a positive charge is present in the oxide, this charge is also reduced. We show that these two effects are independent.

In this paper it is investigated the influence of two polycide processes using WSi2 chemical vapor deposition (CVD) or TaSi2 deposition by sputtering on the integrity of wet and nitrided tunnel oxides (tox= 6.6 nm) used in Electrical Erasable Programmable Read Only Memory (EEPROM) under negative Fowler Nordheim electron injection (FNEI). It was confirmed that the nitridation reduces the generation rates of defects created by FNEI (interface states, neutral traps, positive and negative charges) and the stress induced leakage current (SILC).This reduction is more pronounced when TaSi2 is used rather than WSi2. In sputtering TaSi2 process compared to the CVD WSi2 one, it was observed : (i) - the generation of positive charges and the SILC are higher while the generation rates of interface states and negative charges are smaller ; (ii) - the generation rate of neutral traps is higher in wet oxide while it is smaller in nitrided oxides. Whatever the polycide process, the generation of the different types of defects created by FNEI is reduced by increasing the nitridation temperature while the SILC is increased.

A thorough SILC characterization by using MOSFET induced substrate current is for the first time developed. Based on obtained results, it is argued that a model consisting in a electrode-limited conduction, as the Fowler-Nordheim emission, cannot explains thin-oxide SILC results, while a bulk-limited trap-assisted transport well fits experimental data.

The reversibility of charge buildup and SILC generation in thin oxides subjected to successive stress/anneal cycles is investigated. It is demonstrated that in thin oxides both electron trapping and SILC are nearly fully reversible degradation processes having a generation kinetics almost unchanged after several stressing/annealing cycles. The annealing kinetics of the SILC is likely associated to the out diffusion of charged defects (possibly trapped holes or H+) whose characteristics (diffusivity, activation energy) are independent of the oxide thickness. Moreover correlation between electron trapping and SILC generation has been studied.

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.

This study presents a diagnostic technique for projecting gate oxide reliability and device reliability from the correlation among four kinds of lifetime prediction methods which are experimentally characterized by TDDB, F-N degradation, SILC and hot carrier degradation. It has been found that there exists close correlation between gate oxide degradation and device degradation. Therefore, this technique can be used to evaluate how much the process induced degradation of gate oxide effects on the device degradation.