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High-frequency organic dielectric substrate materials have been widely applied in the fabrication of FCBGA (Flip Chip Ball Grid Array) substrates due to their excellent characteristics of high-speed signal transmission. However, their higher coefficient of thermal expansion (CTE) causes the CTE mismatch between the chip and substrate to increase. High-temperature heating during the reflow soldering process intensifies the thermal mismatch within packaging structure, causing severe warping of the substrate, thereby reducing the yield and subsequent reliability. This study adopted a flatness analyzer and scanning electron microscope (SEM) to characterize the package deformation and micromorphology, and found that the substrate warped after reflow soldering, which caused defects such as chip cracks and micro-bump delamination. A fine finite element simulation model was constructed based on the structure of the experimental sample, and the structure deformation during the soldering process was simulated. An accurate finite element simulation model was constructed based on the structure of the experimental sample to simulate the deformation process of substrate during reflow. Research results show that the constraint of the chip on the substrate during the soldering process is the main factor affecting the thermal deformation mechanism, and the deformation can be suppressed by adding stiffener. This research benefits to the design of FCBGA high-density packaging. • A fine model on the deformation behavior of high-density FCBGA packaging structure was built. • Substrate warpage leads to defects such as crack and delamination in the package during reflow. • The deformation mechanism of substrate during reflow was analyzed. • Adding stiffener improves the rigidity of the substrate and suppresses its warpage. [ABSTRACT FROM AUTHOR]

HgCdTe based infrared focal plane array (IRFPA) continues to be the best performing sensor for imaging infrared seeker systems. A detailed study on the flip chip bonding is described for an improvement in the performance and reliability of FPA under stringent thermal and mechanical cycling load. HgCdTe material has a limitation in the bonding temperature and pressure to preserve the detector performance. Process of thermo-compression bonding is developed here for a large format HgCdTe detector array with ultra-fine pitch. Flip-chip bonding under ultra-low force of 4.6 × 10−4 N/bump is achieved with minimum residual stress and it protects the HgCdTe photo-diodes from dislocation circuit multiplication after hybridization. This thermo-compression process is directly usable for other materials such as InSb, T2SL and InGaAs etc. with due consideration of the material's properties like Young's modulus, coefficient of thermal expansion, Poisson ratio and mechanical strength. HgCdTe FPAs with the optimum bonding parameters are packed in detector-dewar-cooler-assembly (DDCA) and tested for stringent thermal shock, mechanical shock and random vibration process. The fatigue life of 104 thermal cycles is achieved to make suitable for fail safe operation. HgCdTe FPA will have a life span of 13 years (if it is cooled down twice on each day) which is more than the vacuum integrity shelf life of a sealed DDCA. • Issues and their solution of thermo-compression bonding for HgCdTe based FPA with small pitch size. • Optimum bonding parameters provides interconnection of > 99.5 % in FPA. • Fatigue life of 104 thermal cycles achieved for fail safe operation of IRFPA. • HgCdTe based 2 K × 2K FPA (pitch size of 5 μm) is feasible with tolerable misalignment and stress using optimum bonding parameters. [ABSTRACT FROM AUTHOR]

Semiconductor devices are commonly encapsulated with Epoxy-based Moulding Compounds (EMC) to form an electronic package. EMC typically occupies a large volume within a package, and thus, governs its thermomechanical behaviour. When exposed to high temperatures (150 °C and above), electronic packages predominantly show oxidation of the outer layer of EMC. Oxidized EMC exhibits notably different material properties, resulting in a modified deformation pattern of a thermally aged package under varying thermal loads. As the oxidation layer grows in thickness, its mechanical properties also evolve, indicating distinct phases of the oxidized material at different stages of thermal ageing. Reflecting these changes (i.e. , the current state of degradation) into a Finite Element (FE) model-based analysis can provide better insights into failure prediction and component reliability. It requires updating the geometry and material behaviour as a function of ageing. This paper presents a systematic procedure to build a continuously updated physics-based Digital Twin of a thermally aged flip-chip package that can represent intermediate oxidation stages. First, experimental measurements are carried out to quantify the growth of the oxidation thickness at 150 °C and a diffusion-dominant mathematical model is proposed. Then, an accurate geometry of the test package is prepared with a parametric outer layer from all exposed sides of EMC to represent the oxidized layer at different stages of thermal ageing. Next, the experimental characterization of a few partially oxidized EMC specimens is done, and analytical methods are utilized to extract the thermomechanical properties of the oxidized EMC at different stages of ageing. Experimental warpage data of aged test packages are utilized to verify the defined material-model parameters that represent curing shrinkage, thermal expansion, glass transition, and corresponding elasticity moduli of the oxidized EMC at select stages of ageing. Then, a workflow to establish continuity in the material model is presented. Finally, the developed Digital Twin is utilized for an FE analysis to study the change in the trend of out-of-plane package deformations as a function of several stages of EMC oxidation. [Display omitted] • Three-step modelling procedure to represent thermo-oxidative changes in EMC. • Six-parameter material behavioural model of EMC at different stages of oxidation. • Thermal ageing enlarges package deformation (warpage) with a temperature-delay. [ABSTRACT FROM AUTHOR]

The development of innovative power electronics solutions for automotive applications introduces new reliability requirements for electronic assemblies and interconnection technologies. Many of the reliability methods used in power electronics require extensive experimental data, resulting in long product design cycles. This work focuses on developing a simulation-driven approach to assess the solder joint reliability of a discrete silicon carbide MOSFET by monitoring its degradation under power cycling in the thermal and thermo-mechanical domains using the thermal resistance of the stack as a failure metric. Active power cycling tests are performed to determine the loading condition at which end-of-life is reached due to a 20 % increase in thermal resistance. Numerical analysis using finite element simulations is conducted to gain a physical understanding of the failure criterion, allowing to monitor solder degradation based on the thermal resistance and to pinpoint failure at individual interconnects within a solder bump array. The proposed methodology aims to accelerate the quality assurance and product qualification processes of discrete power electronic devices. • Activation of 2nd level solder degradation in a discrete SiC MOSFET package under active power cycling. • Formulation of a simulation-based correlation between the thermal resistance of the stack and the number of damaged joints within a solder bump array. • Identification of failed solder bumps when the end-of-life condition is achieved through finite element analysis. [ABSTRACT FROM AUTHOR]

In recent years, silicon carbide (SiC) semiconductors have gained traction in high-performance power devices due to their ability to operate at high temperatures (above 200 °C). However, traditional interconnection materials are not sufficiently reliable at such elevated temperatures. Typically, in power devices, thick Al wires with diameters of 200 μm or larger are commonly used to bond Al electrodes of semiconductor chips to their corresponding Cu leadframes or substrates. Nevertheless, the low melting point of Al can lead to recrystallization at high temperatures, thereby raising concerns about reliability and a decrease in wire strength and fatigue properties. Although thick Cu wires with higher melting points have been explored as potential solutions, their high hardness and susceptibility to work hardening during bonding can damage the chip beneath the bonding area, making them impractical. In response to these challenges, we investigated the use of thick Ag wires. However, direct bonding of thick Ag wires to Al pads can form intermetallic compounds (IMC) in the bonding area, leading to concerns about decreased reliability. To address this issue, we experimented with a bonding method that utilized thick Ag wires on Ni pads. In this study, we evaluated the reliability of thick Ag wire bonding under various stress conditions, including high-temperature storage tests (HTST) and temperature cycling tests (TCT). Our results showed that thick Ag wire bonding on Ni pads exhibited high bond strength and prevented IMC formation after HTST. Nonetheless, bond failure of the Ag wires could occur after TCT due to the mismatch in the coefficient of thermal expansion (CTE) between the Ag wire and SiC chip, particularly under extremely severe TCT conditions. We found this issue could be mitigated by introducing a soft metal layer, such as Al, between the Ni pad and the SiC chip. This reduced internal stress and enabled the device to pass TCT under harsher conditions with reliable performance. • SiC semiconductors for high-temperature applications • Challenges with traditional bonding materials • Exploration of thick Ag wires • Improved reliability with Ni pads • Addressing thermal expansion mismatch [ABSTRACT FROM AUTHOR]

Because of the demand for high-speed and broadband networks, 5G technology has paid much attention. On the one hand, due to the transit frequency of 5G, which is 450 MHz ~ 6GHz and 24 GHz ~ 52 GHz, the RF component has to deal with a higher frequency than previous communication. On the other hand, a massive high-power channel is required for some applications, like wireless communication base stations, military applications, satellite communication, and TV broadcasting. Therefore, GaN has become a good choice for high-power and high-frequency RF applications. In GaN RF chips, electrically conductive adhesive (ECA) is a key component that restricts heat, electrical conductivity, and reliability. This research studied two ECAs in the die attach process of a 5G base station RF amplifier chip, ABP 8068TA from LOCTITE Corporation and ASP 295-09P9 from Heraeus Group. During the research, ASP 295-09P9 has different die shear performance for GaN and GaAs die. After troubleshooting, operation error, such as the uneven spread of ECA and height of ECA, is excluded. By testing the wafer back surface, it is found that both GaN die and GaAs die back are pure Au, but GaAs die back's roughness is 0.049um, which is rougher than GaN's (0.032um). It is reasonable to assume that a smoother surface is a disadvantage for the necking mechanism. • Two ECAs were investigated in the GaN die attach process of a 5G base station RF amplifier chip. • In the die attach process of this chip, ECA is applied between pure Au die back and ENEPIG on substrate top. • ASP 295–09P9 shows better reliability in temperature-changing application. [ABSTRACT FROM AUTHOR]

Copper nanoparticles (CuNPs) sintering for flip-chip interconnects is a promising solution for 3D and heterogeneous integration to overcome the limitation of solder materials. To this end, we perform the photolithographic stencil printing method to pattern CuNPs, and the form of flip-chip interconnects is completed after CuNPs sintering process. This paper aims to study the effect of sintering processing parameters (time, pressure, temperature) on the mechanical properties of CuNPs bumps when applying the novel method to approach the Cu interconnects. We fabricated seven groups of specimens of sintered CuNPs bumps, built with a diameter of 100 μm and sintered. The nanoindentation tests assessed the mechanical property to get Young's modulus and hardness. Results clarify that Young's modulus is strongly affected by pressure. An suggested combination of parameters (the 25 MPa and 260 °C for 15 min) give the highest modulus of 126 GPa and the hardness of 1.76 GPa. Moreover, the observations by scanning electron microscopy (SEM) reveal the microstructure and porosity evolution versus different processing parameters. • Nanoindentation tests micromechanical properties of sintered copper nanoparticles. • Modulus and hardness are affected by sintering parameters. • The microstructure and porosity evolution depended on processing parameters. [ABSTRACT FROM AUTHOR]

In this paper, a parameter driven monitoring model is introduced, in which a flip-chip LED module was investigated during a power cycling test. This approach was investigated to develop a monitoring model to describe thermally induced solder fatigue as root cause of flip-chip failure in a power cycling test. As monitoring parameter the thermal resistance of the LED module was used, which was determined by thermal impedance measurements of the whole LED module, as well as for each LED chip itself. Further analyses of the occurring temperature at the LED junction recorded of each chip during the power cycling test were used to generate a prediction model. The evaluation of the temperature change allowed to forecast the number of cycles until failure. [ABSTRACT FROM AUTHOR]

Flip chip technology has been widely used in IC packaging, and the combination of flip chip technology and solder joint interconnection technology has been utilized in the manufacturing of electronic devices universally. As the development of flip chip towards high density and ultra-fine pitch, the inspection of flip chips is confronted with great challenges. In this paper, we developed an intelligent system used for the detection of flip chips based on vibration. Thirty-four features including 18 time domain features and 16 frequency domain features were extracted from the raw vibration data. The support vector machine was employed to implement the recognition and classification of flip chips. In order to improve the classification accuracy of SVM, cross validation (CV) and genetic algorithm (GA) were utilized to optimize the parameters of SVM respectively. SVM, CV-SVM and GA-SVM were applied to classification separately and the results were obtained. By comparison, GA-SVM can recognize and classify the flip chips rapidly with high accuracy. Thus, GA-SVM is effective for the defect inspection of flip chips. [ABSTRACT FROM AUTHOR]

Micro solder bump has been widely used in electronic packaging. Currently a number of flip-chip products are developing towards miniaturization with more I/Os at finer pitch, and defect inspection of the high density package is increasingly challenging. In this paper, the Levenberg-Marquardt back-propagation network (LM-BP) combined with the scanning acoustic microscopy technology was investigated for intelligent diagnosis of solder defect. The flip chips were detected by using a 230 MHz ultrasonic transducer. Solder bumps were segmented from the SAM image. The statistical features were extracted and fed into the LM-BP networks for bump classification. The results demonstrate that LM-BP algorithm reached a high recognition accuracy, and is effective for defect inspection of the micro solder bump. [ABSTRACT FROM AUTHOR]

This paper presents an extensive numerical analysis of the thermal behavior of InGaP/GaAs HBTs for handset applications in a laminate (package) environment. Both wire-bonding and flip-chip technologies are examined. The combination between an accurate, yet fast, simulation capability and the Design of Experiments technique is employed to quantify the impact of all the key technology parameters and explore a wide range of operating conditions. [ABSTRACT FROM AUTHOR]

Flip chip technology has made significant improvements to LED chip on board (COB) packages and modules by reducing thermal resistance compared with traditional wire bonded LEDs. However, one of the critical issues of flip chip packaged LEDs is the reliability of their solder interconnects, which are responsible for the heat transfer to the substrate. Based on a supply switching test, also called power cycle test, a model for monitoring and reliability was done to describe the remaining lifetime and additional the solder fatigue. Therefore, changes in thermal resistance of the LED-module were measured and correlated with solder fatigue of the LED flip chip package. Thermal impedance measurements were performed to monitor the status of the LED-module. Detailed analyses, comparing with the initial state, allow the evaluation of the occurring temperature swing of each LED chip. Single chip analysis combined with a thermal resistance driven monitoring model allows the calculation of remaining lifetime at each time during testing and beyond the first chip failure in a multi chip LED-module. Accordingly, it could be shown that the thermal impedance is a powerful tool for reliability monitoring and failure analysis. [ABSTRACT FROM AUTHOR]

Ever since RoHS was implemented in 2006, Sn3.0Ag0.5Cu (SAC305) has been the primary lead-free solder for attaching electronic devices to printed circuit boards (PCBs). However, due to the 3.0 wt% Silver (Ag) in SAC305, companies have been looking at less expensive solder alternatives, especially for use in inexpensive products that have short operating lives and are used in mild application conditions. This paper reviews new lead-free solder alternatives and the trends in the industry, including SnCu-based solders, SnAgCu solders with Ag content < 1.0 wt%, SnAg solders, and no-Ag low-temperature solders (e.g., SnBi-based solders). The analysis is conducted for reflow, wave, and rework conditions and for packaged and flip-chip devices. [ABSTRACT FROM AUTHOR]

Flip chip thermo-compression bonding (TCB) involves the use of heat and pressure to simultaneously form interconnections for microelectronic packaging. In-situ measurements of thermo-mechanical stresses that arise during this bonding process could provide unique insight to help better understand the TCB process. A 4 mm × 3 mm × 500 μm complementary metal-oxide-semiconductor (CMOS) sensor chip with an 8 × 8 array of Au-bumped sensor pads was developed for this purpose. It was designed to record XYZ force and temperature signals from bump locations, during a simulated flip chip process similar to TCB. In-situ measurements during simulated TCB events proved useful for tilt detection, thermal gradient characterization, and thermal expansion measurements. Further interpretation of the signals proved tilt and other thermo-mechanical effects were induced by thermal expansion mismatches. The most thermo-mechanically stressful stage of bonding was found to occur during thermal transients, specifically during bond head ramping. Further analysis concluded the actual time necessary to heat the bumps was less than 0.5 s. Finally, the lateral thermal gradient across the sensor chip was calculated to be smallest in the central bump locations, and largest in the bump array corners due to warpage, tilt, and heat sink effects of the digital logic region. [ABSTRACT FROM AUTHOR]

A fast low dropout (LDO) regulator based on flipped voltage follower (FVF) with impedance compensation, is presented. This LDO offers stable regulation over wide range of load capacitances starting from 10 pF to 10 nF. It provides an extended load regulation from 100 μ A to 30 mA. This enhancement is achieved by incorporating a voltage combiner stage along with an active feed-forward into the regulating loop. Unconditional stability for wide range of loads is ensured with the help of Miller's compensation with a nulling resistor by the use of on-chip 75 pF capacitor, 4.5 k Ω MOSFET resistor and a feed forward capacitor. The proposed LDO is verified with simulation in 45 nm CMOS process. For an input voltage of a 1.2 V–2 V, LDO offers a regulated output of 1.07 V, with a minimal drop out voltage. Under a load transient of 100 μ A to 30 mA within 1ns of edge time, the undershoot and overshoot are limited respectively to 35 mV and 82 mV, with almost 295 ps of response time. The quiescent current excluding the control voltage generator is 81–112 uA, which provides excellent current efficiency. The simulated PSRR is −42 dB over the band of 10 Hz–10 kHz, −20 dB at 1 MHz over 100 uA–50 mA of load currents also across varying load capacitors of 10 pF–10 nF. The line regulation is approximately 1.35mV/ V and load regulation is around 2 μ V/mA. [Display omitted] • Impedance compensation is a potential technique to extend the stability of an LDO across load currents and varieties of load capacitors. The proposed impedance compensation implemented by a voltage combiner, enhances the loop gain and offers very low output impedance over a wide band width. • The extended BW achieved with the help of proposed impedance compensation helps in improvement in transient response of the orders of pico seconds. • The LDO achieves phase margin of 75 degree, good PSRR while driving upto 10's of nF load capacitors both under heavy and light load currents. [ABSTRACT FROM AUTHOR]

With miniaturization of the interconnect solder bumps, high current density causes serious reliability issues (stress, electromigration etc.) in electronic packages. Through Au stud bumping on the chips and following reflow of solder to produce hybrid interconnects, the eletromigration resistance may be improved by the intermetallics formed inside them due to their barrier effects on the atoms migration. Here, microstructures and reliabilities of Au stud with serial amounts of Sn-0.7Cu solder paste were studied through controlling size of stencil printing aperture. After reflow, AuSn, AuSn 2 and AuSn 4 formed from the surface of Au stud bump to the solder. A layer of (Cu,Au) 6 Sn 5 with thickness of 3 μm existed at the interface near the Cu substrate with a scallop shape similar to Cu 6 Sn 5 . The fraction of intermetallics to the mixed joints varied with the solder amount. Shear strength decreased slightly when comparing with the sole solder joint due to large amounts of brittle intermetallics. Thermal aging resulted in many Kirkendall voids generated at the interfaces of Au stud and the solder, which further decreased the shear strength. The effect of solder amount on microstructural evolution and fracture modes was discussed. The hybrid interconnects showed a good electromigration resistance. [ABSTRACT FROM AUTHOR]

Flip-chip package reliability is greatly improved by encapsulating the solder interconnections between a polymeric encapsulant or underfill. However, thermo-mechanical stresses within such packages often lead to failures initiating in the vicinity of chip and underfill interface. In this study, we present experimental results geared towards measuring and understanding such failure mechanisms. We provide the bulk fracture toughness of the underfill material and interfacial fracture toughness between the underfill material and the silicon die. The bulk and interfacial fracture toughness measurements are performed as a function of temperature. We use the single edge notch bending test to calculate the bulk fracture toughness of the underfill and to measure the interfacial fracture toughness, we use a novel technique referred to as the wedge delamination method. The wedge delamination method provides substantial advantage in measuring the interfacial fracture toughness for brittle materials over traditional methods. Using the wedge delamination method we compare the fracture strength between the underfill and silicon at the front-face and side-wall interfaces. Additionally, the influence of dicing technique on fracture toughness is also investigated. [ABSTRACT FROM AUTHOR]

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented. [ABSTRACT FROM AUTHOR]

Edge effect is a common phenomenon observed in acoustic micro-imaging of microelectronic packages. In this paper, using flip chip package geometry as a test vehicle, finite element modelling is carried out to study the fundamental mechanism of the edge effect phenomenon. C-Line plot technique is developed for the characterization of edge effects in acoustic C-scan images, in particular solder joint C-scan images. Simulated results are compared to experimental results. Results reveal that edge effect generation is mainly attributed to the under-bump-metallisation structure. In addition, through analysis of the C-Line profile of edge effects, the impact of the transducer focal point and the spot size on the edge effect is investigated. Results show that slight off-focus can reduce the severity of the edge effect in which image sharpness is a trade-off. [ABSTRACT FROM AUTHOR]

Flip chip has been extensively used in microelectronic packaging industry. With the trend of solder bumps towards small volume and ultra-fine pitch, defect inspection of flip chips has become more difficult. In this work, we introduce radial basis function networks for detecting and predicting missing solder bumps, a typical defect in flip chips. Eight time and frequency domain features extracted from the flip chip vibration data are inputted to the networks, and flip chips with missing bumps distributed adjacently or randomly are detected and predicted. For the PAC2.1 flip chips with missing bumps distributed adjacently, we distinguish the defective flip chips from the reference one with a 100% accuracy. The flip chips with 1 to 2 missing solder bumps are then trained and detected accurately by the network, and the chip with 3 missing bumps can be predicted exactly as well. After that, we train the network with the data of flip chips with 1 to 4 missing bumps. The network can recognize the number of the missing bumps in these flip chips with a 100% accuracy, and predict 5 missing bumps in the flip chip with the accuracy of 91.7%. For further validation, we use the PB08 flip chips with missing bumps distributed adjacently or randomly for training, testing and prediction, and also obtain high accuracies. These prove the feasibility of using RBF networks for detection and prediction of flip chips with missing bumps in engineering. [ABSTRACT FROM AUTHOR]

The interfacial reactions and failure modes of the solder joints for flip-chip light emitting diode (LED) on electroless nickel/immersion gold (ENIG) and Cu with organic solderability preservatives (Cu-OSP) surface finishes were investigated in this study. The experimental results demonstrate that the interfacial reactions in the Au/Sn–Ag–Cu(SAC)/ENIG and Au/SAC/Cu systems are different but the failure mechanisms of the two types of solder joints are similar during the shear test. For the Au/SAC/ENIG system, the Au layer on the surface finish of the diodes dissolved into the molten solder and transformed into a continuous (Au, Ni)Sn 4 IMC layer at the diode/solder interface during reflow and the interfacial IMC at the solder/ENIG interface is dendritic Ni 3 Sn 4 IMC grains which are surrounded by (Au, Ni)Sn 4 . For the Au/SAC/Cu system, however, no IMC layers can be observed at the diode/solder interface. The interfacial IMC at the solder/Cu interface is (Cu, Au) 6 Sn 5 and a Cu 3 Sn IMC layer at the (Cu, Au) 6 Sn 5 /Cu interface. Tiny (Au, Cu)Sn 4 IMC grains distribute in the solder layer and surround the (Cu, Au) 6 Sn 5 grains. For the two types of systems, the primary failure mode for the cathode is due to the broken of the Si-based insulation layer which led to a high residue stress and poor connection between the Si-based layer and the solder layer. Meanwhile, the failure of the solder joint for the anode is mainly because of the failure of the solder layer under the conductive via. The crack generally forms at this area and then propagated along the diode or the diode/solder interface. [ABSTRACT FROM AUTHOR]

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit's reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits. • We propose ILP-based HLS methods to optimize reliability and energy in ASIC design. • Our models employ full and partial duplication to improve the system reliability. • We use voltage islands as the energy reduction method of choice. • Different versions of the same resources are used to meet the constraints. [ABSTRACT FROM AUTHOR]

Voids in solder interconnects play a crucial role in influencing performance and reliability of solder interconnects, and even lead to the open failure of electronics, especially when high density electric current flowing through the solder interconnects. In this paper, the morphological evolution and migration behaviour of the voids in the solder domain of solder interconnects under electric current stressing is investigated using a developed phase field model. Results show that the surface energy drives the coalescence of voids, and large size voids grow up at the expense of small size ones. The voids migrate along the electric current direction, and the current density distribution and void distribution interactively affect the evolution and migration of the voids. The high magnitude of electric field can potentially induce the open-circuit failure, and the void size is affected by the electric field. Moreover, the voltage across the solder domain increases as the voids migrate to the cathode side. Furthermore, the electric field can promote the void coarsening, and the void migration velocity increases almost linearly with the magnitude of the electric field. • The electric field effect is coupled to a phase field model. • Electric field promotes void coarsening. • Voltage increases as voids migrate to the cathode side. • Effects of electric field on void migration kinetics are characterized. [ABSTRACT FROM AUTHOR]

The flip chip packaging technology uses solder bumps for the electrical connection between the chip and substrate. A two-step procedure is usually used for the flip chip packaging. In the process, underfill material is filled into the gap between the chip and substrate by the capillary force. After that, epoxy molding compound (EMC) is used to overmold the entire assembly in a mold cavity through the process of the transfer molding. On the other hand, the molded underfill (MUF) process performs the packaging at a single step. In the MUF process, the EMC material fills the mold cavity with preplaced flip chip assembly, and finishes the underfill and overmold at the same time. In this study, experiments were performed to study the mechanism of the void formation in MUF. The effect of vacuum on the void formation was investigated. It was found that high quality of vacuum was necessary in order to eliminate the air pocket enclosed during the filling process. For different materials, the required vacuum quality may be different and it is well below the perfect vacuum. [ABSTRACT FROM AUTHOR]

Flip chip packaging technology is widely used in high density assembly and superior performance devices. The solder joints are sandwiched between dies and substrates, leading to the defects optically opaque. Defect inspection of flip chips become more difficult. In this paper, a nondestructive detection method was presented. Ultrasonic excitations were forced on the surface of the flip chips and the raw vibration signals were measured by a laser scanning vibrometer. Eleven time domain features and twenty-four frequency domain features were extracted for analysis. After that, the genetic algorithm was introduced for feature selection and the back propagation network was adopted for classification and recognition. The flip chips were divided into three categories: good flip chips, flip chips with missing solder joints, and flip chips with open solder joints. They are recognized under the features selected by genetic algorithms rapidly and accurately, compared with those under other feature datasets, demonstrating that the approach using genetic algorithms is effective for defect inspection in flip chip packaging. [ABSTRACT FROM AUTHOR]

A dipping method for flux coating is proposed in the paper. Flow process of the flux transferred into the groove is investigated by using an optical detection means. Flow process influenced by gluing speed and viscosity is analyzed by using two indicators including reflective area ratio and flow velocity. Experimental result shows that stably reflective area ratio of glue is associated with gluing speed instead of viscosity; and it decreases with the increase of gluing speed in a same viscosity. The reason is that different gluing speed changes the amount of the glue transferred to the groove. Flow velocity of glue is related with gluing speed, a greater gluing speed leads to greater maximum flow velocity at the same viscosity, which may be due to larger gluing speed gives greater inertial force to the glue. Real chip experiments verified the feasibility of this method. [ABSTRACT FROM AUTHOR]

This paper investigates the effect of void percentage in the solder layer on the shear strength and thermal property of DA3547 packages by SAC soldering technology. X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages. Furthermore, packages with lower void percentage showed a lower junction temperature based on the results of IR test and finite element simulation. The temperature difference due to the effect void percentage shows a correlation with the input power. For the DA3547 packages studied in this research, voids show limited influence on the junction temperature under 50 mA, the typical current recommended by Cree. [ABSTRACT FROM AUTHOR]

Power distribution in both 2D and 3D integrated circuit (IC) devices becomes one of the key challenges in device scaling, because the on-chip power dissipation becomes significantly severe and causes thermal reliability issues. In this study, the process solution to resolve the on-chip power dissipation by improving power distribution was investigated through newly designed power bumps called ABL (advanced bump layer) bumps. Rectangular-shaped Cu ABL bumps were fabricated and bonded on Si substrate using flip chip bonding process. The bump height difference in signal and ABL power bumps, bonding interface, and electrical resistivity of flip chip bonded structure were evaluated. The lowest electrical resistivity of Cu ABL bump system was estimated to be 3.3E-8 Ω m. The process feasibility of flip chip bonded structure with Cu ABL bumps has been demonstrated. [ABSTRACT FROM AUTHOR]

Highlights: [•] First validated simulation of solder balls with plastic core. [•] Determination of the influence of different geometrical parameters. [•] Electromigration in the solder material with a copper surrounded plastic core. [Copyright &y& Elsevier]

Highlights: [•] We have studied the reliability of flip-chip assemblies with 100-μm pitch SAC305 solder bumps. [•] We show that the assemblies will last more than 4000 cycles under thermal shock experiments. [•] We show that there is no dual intermetallic compound (IMC) near the die pad. [•] We show that the solder cracking under thermal shock occurs outside of the IMC, not inside the IMC. [Copyright &y& Elsevier]

Highlights: [•] Defects detection using active thermography is proposed. [•] Temperature distribution is acquired by the infrared imager. [•] The results in thermograph between defects and reference are very different. [•] The results in temperature history between them are very different. [•] Different kinds of chips with different sizes are tested. [ABSTRACT FROM AUTHOR]

Chip resistors are the most common and most frequent components in all electronics. Voids are formed by outgassing during solder reflow. Excessive voids influence the electrical and thermal conductivity of the solder joint and hence reduce its reliability. Therefore, in this study, we propose a scheme combining Residual Multiscale Skip Connected Net (RMSC-Net) and Recurrent Convolutional Network (RU-Net) to accurately detect the voids and solder joints of the X-ray images of the chip resistor. We first develop an RMSC-Net for void segmentation of X-ray images. RMSC-Net combines residual with multiscale skip connections. Residual learning solves the problem of gradient dispersion by learning the difference between the target and input values. The proposed multiscale skip connection combines multiple high- and low-resolution feature maps to realize multilayer feature perception of voids. Then, we deploy RU-Net with recurrent convolution modules to apply the chip resistors' solder joint segmentation. Experimental results demonstrate that the overall performance of RMSC-Net and RU-Net is better than other methods in detecting voids and solder joints of three different types of chip resistors. RMSC-Net achieves average SE gains of 2.70 and 2.25 points over UNet++ and FedDG, respectively. The average PR of RU-Net is 0.34 and 0.61 points higher than that of UNet++ and FedDG, respectively. • A detection scheme that combines RMSC-Net and R-UNet to detect voids and solder joints in chip resistors is proposed. • A RMSC-Net is developed for micro-voids segmentation of CT images. • We present multi-scale skip connections to fuse different levels of features. • The residual is introduced to solve the problem of gradient dispersion or gradient explosion. • R-UNet with recurrent convolution modules is adopted to detect the edges of solder joints accurately. [ABSTRACT FROM AUTHOR]

Abstract: With the adequate bonding parameters, a bonding load of 930gf, an ultrasonic power of 20.66W, a bonding temperature of 200°C and a bonding time of 0.3s, a sound bond with sufficient die–shear force was achieved in chips thermosonically bonded directly onto copper electrodes with a 0.5μm-thick nickel layer. After chips thermosonically bonded onto copper electrodes, the reliability of temperature cycling test (TCT) and high humidity/high temperature (HH/HT) test was evaluated. The reliability of TCT and HH/HT test demonstrates that gold bumps were firmly bonded onto copper electrodes over the flex substrates for subjected various test durations. Therefore, the reliability of TCT and HH/HT test for gold bumps thermosonically bonded directly onto copper electrodes should not be an important issue. During TCT, thermal stress at the interface between the gold bumps and bond pads of silicon chips caused crack at the interface. That is, the TCT degraded the die–shear forces of chips and flex substrate assemblies. The reliability of the TCT in chips thermosonically bonded onto flex substrates was dependent on the severity of crack. Similarly, crack and blisters that occurred at the bonding interface between gold bumps and bond pads of silicon chips after HH/HT tests of varying durations deteriorated the die–shear forces. Moistures penetrated into deposited layers of bond pads, deposited layers lost their adhesion, and cracks and blisters were formed as increasing the test durations. The reliability of TCT and HH/HT test must be improved to prevent crack at the bonding interface between the gold bumps and bond pads and to prevent moisture from penetrating into the deposited layers of bond pads, respectively. [Copyright &y& Elsevier]

Abstract: Sensor interconnection achieved with Flip Chip (FC) technology and most particularly with Anisotropic Conductive Adhesive (ACA) is a very attractive technique, in achieving a Direct Access Sensor (DAS), in a swallowable diagnostic sensing capsule. This paper describes the work carried out to mechanically characterise the ACA joints when they are inserted in the capsule to determine the smallest capsule diameter that could be used without imparting excessive stress on the interconnect in the DAS integration process for a specific substrate and chip design. Three point inward bending was used to study the effect of the mechanical loading on the joints during the insertion process. The results showed that the insertion force linearly increased and leveled off at a, low friction, constant value. The spring constant of the linear region in a 23mm was 0.2729N/mm and increased to 1.5N/mm for the 15mm diameter hole. It showed that the spring constant decreased linearly as the diameter increased, signifying that for the same distance, less force will be required in a larger diameter hole than in the small diameter holes. During insertion the stress in the assembly, was higher towards the centre of the chip and the window than at the edge of the chip and the ACA fillet. This was characterised by it exhibiting lower voltage values measured in the partial daisy chains that were close to the window rather than the ones that were situated away from the window. The insertion test suggested that the 23mm diameter hole would be the smallest suitable hole for insertion of this assembly. Failure analysis revealed that the depression and the wide crack close to the window imply that the stress was high in this region. The cross sectional analysis showed that failure occurred within silicon/silicon chip pad and that the ACA contacts form a strong joint and was able to withstand the insertion force required to secure the ACA sensor in place before encapsulation. [Copyright &y& Elsevier]

Abstract: Numerical methods like the finite element (FE) method are often used to evaluate the reliability of electronic packages. However, the accuracy of non-linear numerical analyses should be confirmed by experimental measurements. In this study, we evaluated the strain distribution in flip chip (FC) packages with multi-layered printed circuit boards (PCBs) by combining the digital image correlation method (DICM) and the non-linear FE method, considering the viscoelasticity of resins and the elastoplasticity and creep of solder alloy. Four types of FC package consisting of two types of buildup (BU) resin and two types of underfill (UF) resin were evaluated. The distributions of strain on the cutting sections of FC packages were measured using the DICM with microphotographs obtained by a confocal laser scanning microscope (CLSM). The strain measurements showed that the UF resin with the low coefficient of thermal expansion (CTE) reduced thermal strain around a solder bump, and the BU resin with the low CTE reduced the strain concentration along the interface between a Si chip and a solder bump. We performed the non-linear FE analyses while taking into account the viscoelastic Poisson’s ratio of the UF resin and the constant instantaneous Poisson’s ratio. The result of the FE analyses with the constant instantaneous Poisson’s ratio did not correspond with the strain measurements using the DICM. The normal strain in a solder bump was less than that obtained by the measurement, and the direction of a shear strain band in a solder bump was different from that measured using the DICM. On the other hand, the FE analyses considering the viscoelastic Poisson’s ratio showed good agreement with the strain measurements using the DICM. The strain measurement using the DICM improved the accuracy of the non-linear FE analysis of microelectronic packages effectively. [Copyright &y& Elsevier]

Abstract: As microelectronic industry develops 3D IC on the basis of through-Si-vias (TSV) technology, the processing and reliability of microbumps, which are used to interconnect the stacking chips, is being actively investigated. Due to the reduction in size of microbumps, the diameter is about one order of magnitude smaller than that of flip chip solder joints, and the volume is 1000 times smaller. Its microstructure and in turn its properties will be anisotropic because the number of grains in a microbump becomes very small. Its statistical failure will have a wide distribution because of anisotropy, including early failure. This review addresses this issue and the remedy. [Copyright &y& Elsevier]

Abstract: The reliability of solder joints is a critical element for the successful application of flip chip technology. This paper presents a nondestructive inspection method using modal analysis combined with image processing for the defect detection of flip-chip solder joints. Simulations are implemented to explore the feasibility of applying the chip modal shapes and resonance frequencies for defect detection. In experimental investigations, the signal generator and power amplifier are applied to drive the capacitive air-coupled ultrasonic transducer to produce continuous ultrasonic waves for exciting the test chips. The vibration responses of the chips are measured by the laser scanning vibrometer in order to reconstruct modal shapes and extract resonance frequencies. The chip modal shapes are analyzed by virtue of image processing technique, and the resonance frequencies are investigated through frequency spectra. The results reveal that the defective chips can be distinguished from the good chips by the modal shape differences represented by the characteristic angles, and the chip resonance frequencies can also serve as an indicator for defect detection, which prove the feasibility of this method. [Copyright &y& Elsevier]

Abstract: Acoustic Micro Imaging (AMI) techniques have been widely used as a non destructive evaluation (NDE) tool in evaluating both microelectronic packages and solder joints. However, there are a lack of analysis tools and automated inspection techniques to facilitate the inspection process. This paper presents a novel approach to extract the solder joint’s features from ultrasound images for automated solder joint assessment. The proposed method consists of three stages: solder joint detection, feature extraction, and defect evaluation. Firstly, a gradient based circular Hough transform is employed to detect the solder joints in acquired ultrasound images. Subsequently, feature extraction is carried out by a radial gradient based region growing algorithm. Finally, defect evaluation is achieved by analysing the variation of the image features automatically. Cross-sectional analysis was performed to validate and evaluate the performance of the solder joint inspection system. The results show that image features obtained by the system can be used easily to distinguish between a healthy and fractured joint, thus confirming the feasibility of the automated AMI inspection technique. [Copyright &y& Elsevier]

Abstract: The recent uses of microelectronics as sensors or control devices at high-temperature ambient increase the rate of visco-plastic degradation of solder joints of their components. The response of solder bumped joints to the induced thermal load culminates in plastic strain which over many cycles may accumulate damage in the joints, subsequently leading to their fatigue failures. Finite element modelling is employed to investigate the impact of static structural factors of flip chip (FC) assembly on its solder joint damage at high-temperature excursions. This paper discusses results of a modelling study focused on effects of component stand-off height (CSH) and intermetallic compound (IMC) on static structural integrity of lead-free solder joints in a flip chip FC48D6.3C457 package which is cycled between −38°C and 157°C temperatures. The result analysis is based on accumulation of damage indicators such as stress, strain and plastic work density in the solder joints. The accumulated damage was used to predict the thermo-fatigue life of different architectures of the FC assembly. It was found that the fatigue life of the joint assemblies decrease exponentially as the component stand-off height decreases in a cubic function. Based on our research results, it is proposed that the size of diameter of bond pad defined by solder mask on printed circuit board (PCB) should not exceed 110% of the size of diameter of bond pad at the chip side. [Copyright &y& Elsevier]

Abstract: Flip-chip packages with a 40nm wafer node with ELK (extreme low-k) dielectric are prone to early low-k delamination beneath the solder joints right upon flip-chip bonding before underfilling. The chip-package interaction (CPI) therefore becomes a design consideration for flip-chip packages with a 40nm wafer node and beyond. In this work, finite element analyses were carried out to explore CPI in process of a 40nm ELK flip-chip package with SnAg solder joints. Results indicate that a small ratio of polyimide (PI) opening over under bump metallurgy (UBM) size, a thick redistribution layer (RDL) or RDL sandwiched with PI for stress buffering, a thick substrate core, and a thin die are directions to follow in order to minimize the ELK delamination potential. [Copyright &y& Elsevier]

Abstract: Thermosonic flip chip (TSFC) bonding is a developing area-array microelectronic package technology. To better understand the bonding formation mechanism, a dynamic finite element model of the TSFC bonding process was developed, where the soften effect caused by the heat stage and ultrasonic vibration was considered in the constitutive relation of the gold bump. With this model, the strain evolution processes for the bump and the bump/pad interface were obtained and compared, and it was found that the deformation of the bump is always larger than that of the bonding interface; this may decrease the Allowable I/O pitch and bonding strength. To increase the ratio of the strain of the bonding interface to that of the bump, parameter studies are carried out, and the effects of ultrasonic vibration amplitude, bonding force, and static friction coefficient on the plastic deformation and strain distribution on the bump and the bump/pad contact interface were studied. Based on the simulation results, the effects of the parameters on the strain distribution were obtained, and some recommendations for parameter optimization are given. This FE simulation study may assist in process window development for fine pitch TSFC bonding. [Copyright &y& Elsevier]

Abstract: The determination of the real value of damage/plastic work density in solder joints from computer numerical modelling and its usage in fatigue life prediction models based on accumulated energy density is critical to improving the accuracy of predicted life of solder joints. Commercial ANSYS software based on three-dimensional finite element analysis (FEA) was employed to investigate damage of bonded materials of lead-free solder joints in a flip chip (FC48D6.3C457) mounted on a printed circuit board (PCB). The trend behaviour of accumulated damage and fatigue life per cycle over many accelerated thermal cycles (ATCs) are also studied. The solder bumps deformation is modelled using ANAND’s visco-plasticity and the performances of all other materials in the assembly were captured with appropriate material models. It was observed that the difference in stress magnitude and amplitude between inter-metallic compounds (IMCs) at the die side and solder bulk was highest and the presence of IMC in the joints increases bump damage which occurs in three stages during temperature cycle loading. These results demonstrate that while IMC impacts solder joint reliability, the bond at interconnect between IMC at the die side and solder bulk is most vulnerable to fatigue crack initiation and propagation. A new methodology to find accurate solder joint damage is presented. The findings show that average damage from cycle of hysteresis loop stabilisation to cycle of onset of tertiary damage demonstrates potential of being adequate in determining magnitude of the solder joint damage. However, considering that damage evolution is in three-phase, we propose the use of polynomial function to estimate plastic work damage in FC solder joints. [Copyright &y& Elsevier]

Abstract: Our case study concerns flip-chip devices, assembled on Printed Circuit Board with direct bumping, failing catastrophically under thermal cycles stress. The failure analysis highlighted a deep crack in silicon, systematically located under a particular bump. We show the path followed to understand failure mechanism by means analyses performed at various back-end process steps, up to wafer inspection. Micro-cracks in passivation layer were found, generated only in the spacing between minimum width stripes of last metal layer. Fixed the multiple passivation layer, necessary to protect the devices up to bumping process manufacturer, layout study and 3D simulator stress evaluation, allowed us to identify the metal stripe width as the “key” factor. The implemented solution was minimum metal 4 stripes widening. The devices with new layout were submitted to thermal cycles stress, resulting in zero failures (up to 500 cycles), versus 30% of failure rate (after 100 cycles) of first layout version. [Copyright &y& Elsevier]

Abstract: A new experimental method to predict reliability for ACA type packages under temperature cycling is developed and proposed. The method introduces a new damage parameter that can be easily measured by experiment. It is proved that the linear elastic parameter, dw/dT which represents the rate of change of chip warpage with respect to temperature, efficiently reflects the common failure mechanism of ACA type packages, the interfacial delamination between the chip and the adhesive. It is demonstrated, both experimentally and numerically, that the size of delamination affects the warpage behavior of the chip. The dw/dT of the chip is monitored in real time using laser interferometers under thermal fatigue cycles up to 3000. The gradual decrease in warpage due to progressive increase in delamination is clearly emerged. As a result, a reliability curve that can predict the size of delamination and remained life is obtained. The new long-term reliability prediction method developed in this study can be applied to various advanced packages, e.g. underfilled flip–chip or TSV stacked chip packages, that embrace interfacial delamination as primary failure mode. [Copyright &y& Elsevier]

Abstract: The purpose of this study is to investigate the thermal behavior at the die-attached interfaces of flip-chip GaN high-power light emitting diodes (LEDs) using a combination of theoretical and experimental analyses. The results indicate that contact thermal resistance increased dramatically at the die-attached interfaces with aging time and stress, degrading the luminous flux. The junction temperature and thermal uniformity of the flip-chip structure both strongly depend on the arrangement of gold bumps. Local hot spots effectively reduce light output under high electric and thermal stress, influencing the long-term performance of the LED device. The results were validated using finite element analysis and in experiments using an infrared and an emission microscope. A two-step thermal transient degradation mode was identified under various aging stresses. A simulation further optimized the bump configuration that was associated to yield a low junction temperature and high temperature uniformity of the LED chip. Accordingly, the results are helpful in enhancing the performance and reliability of high-power LEDs. [Copyright &y& Elsevier]

Abstract: Flip chip bump cracking was observed after Si die attach reflow on the organic substrate of a module package. High-lead bump and eutectic SnPb cladding were used on Si die and the substrate sides, respectively. The reflow peak temperature was 260°C for compatibility with passive components attach using lead-free solder. Flip chip bump cracking occurred at high-lead solder close to the die side. The cracking was eliminated by lowering the reflow peak temperature down to 225°C. Main cause of the cracking at 260°C reflow was attributed to the extensive Sn diffusion into high lead bump. This decreased the melting point of the high-lead solder around the die side, which in turn worsened the adhesion between solder and die due to the coexistence of solid and liquid. Diffusion length estimation showed both of the liquid- and solid-state diffusions of Sn. Crack gap in the solder bump was consistent with thermal expansion mismatch between Si die and organic substrate. The bump cracking was mitigated by use of 225°C reflow, limiting Sn diffusion and providing a good integrity of high lead bumps on die side. [Copyright &y& Elsevier]

Abstract: The paper aims at optimization of the residual thermal–mechanical behaviors of a novel Flip Chip (FC) technology during and after the fabrication process. In this study, we first introduce the novel adhesive-typed FC packaging technology, consisting of a nanocomposite film for anisotropic electrical conduction and a nonconductive paste (NCP) for developing NCP joints. In the optimization work, the material and geometry properties and the bonding process parameters are considered as the design parameters, and the constraints on the residual behaviors and the design parameters are included. To deal with the multi-criteria design optimization problem, an effective metamodeling-based design optimization scheme is applied, which integrates parametric finite element (FE) analysis, a response surface methodology (RSM) and an updating scheme. Moreover, to assess the residual behaviors, a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death–birth” meshing scheme is carried out. The validity of the process-dependent FE simulation methodology is confirmed through experiment. Finally, two design practices are performed, and the calculated optimal designs are compared with each other and with the original design. It turns out that the present optimization methodology can be very effective and robust in seeking the optimal design of the FC technology with a better residual thermal–mechanical performance after the NCP bonding process. [Copyright &y& Elsevier]

Abstract: At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the packaging. If we assume just a difference of 1°C across a micro-bump of 10μm in diameter, the temperature gradient is 1000°C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what we have known from flip chip technology. [Copyright &y& Elsevier]

Abstract: This study investigated the dynamic variations of flow and meniscus during underfill process using flow visualization techniques to understand physics of capillary flows. For the quantitative flow visualization, a high speed micro particle image velocimetry (μPIV) was applied to a transparent flip chip specimen with arrayed bump structure. As an underfill liquid, glycerin was filled into the flip chip specimen by capillary action. The present visualization technique offers time-varying movement of meniscus and phase-locked velocity fields frozen to the meniscus position. To observe the dynamic contact angle between parallel plates, an in situ measurement technique was developed in the present study. Then, the filling time was compared with analytical models. From this experiment, it was found that the meniscus velocity and the contact angle vary in-phase according to the position of meniscus. The phase-locked velocity fields show velocity gradients on the meniscus surface which gives rise to the breakdown of equilibrium contact angle. Consequently, the detailed filling time has different behavior from the analytical models. [ABSTRACT FROM AUTHOR]

Abstract: Glue is widely used to improve the reliability of ball grid array (BGA) under mechanical shock and vibration. Although it has been demonstrated to have a positive effect on the reliability of BGA under mechanical impact, it can have adverse effects on BGA under thermal cycling. This paper investigates the effect of glue on the reliability of BGA under thermal cycling using both experimental and numerical methods. The digital image correlation (DIC) technique was used to obtain the thermal mechanical behavior of the package. The experimental results explain in detail how the glue negatively affects the reliability of the BGA. Furthermore, a finite element analysis was performed and its results were verified with experimental results. A numerical parametric study was carried out on various mechanical properties, configurations of the glue, and introduction of a stiffener using the validated FEM model. The results show that the reliability of BGA strongly depends on geometries and material properties of the glue. Based on the results, a guideline of glue selection for BGA reliability under thermal cycling is formulated. [Copyright &y& Elsevier]