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A PoF approach to mitigating infant mortality is proposed which includes (1) conducting reliability capability and product maturity analyses; (2) identifying defects through non-destructive analysis, if possible; and (3) developing electrical tests to screen out early failures. The non-destructive analysis approach was outlined using die attach in a power module as a test bed, while the electrical testing approach was outlined using film capacitors. More data is being gathered to validate that the electrical test provides an early differentiation of change in capacitance over time between good and defective capacitors.

For automotive qualification of Integrated circuits (ICs), multi-temp testing is required by AEC-Q100. In this paper, we demonstrate the importance and necessity of this multi-temp testing in automotive qualification and zero defects program. During the qualification of one of our new products, we found that all samples could pass electrical testing at room temperature after high temperature operating life test, but a few of them failed at hot temperature. One transistor in the circuit was found to have large leakage current. Only at hot temperature, this leakage current was increased (>50 μA) and the fail was detected during hot electrical testing. Root cause was identified and design error is corrected before the release of the product. No failures are observed anymore.

A wafer level in situ accelerated ageing method is proposed. A development of in situ techniques for building-in approach to reliability is introduced, because “ in situ ” does not refer to the electrical testing during the ageing but it is referring to the ageing process itself. A He-Ne laser irradiation of the reverse biased junction is used for accelerating the local degradation by deep level generation currents - the hot spots formation. The efficiency of the method for wafer reliability monitoring was experimentally proved on RF power transistors.

This paper is a review of the most important results on failure physics of integrated circuits, as a synthesis of what has been recently encountered in the literature concerned with these problems. In the first part of the paper systematization of failure modes in integrated circuits is accomplished so that all failure modes are divided into four groups according to their origin: (i) failure modes associated with chip; (ii) failure modes resulting from leads and bonds; (iii) failure modes associated with encapsulation; and (iv) failure modes due to external effects and overstress. Also, some typical failure mode distributions of different types of integrated circuits are given and the effects of the changeover from LSI to VLSI on failure mode distributions are discussed. In the second part of the paper the most important tests for enhancing of the failure modes are enumerated and relationship between the failure modes and the tests for their detection is given. Also, the role of electrical testing by the curve tracer and the accompanying analytical techniques (scanning electron microscopy, transmission electron microscopy, electron beam microprobe, Auger electron spectroscopy and X-ray radiograph) are discussed. Finally, the diagnostic technique is described which, using simple electrical testing by the curve tracer and some tests for enhancing of the failure modes (high temperature bake and high temperature burn-in), enables simple detection of integrated circuit failure modes. In the third part of the paper a survey of test structures for failure analysis of integrated circuits is made. Test structures are divided into three groups according to the kind of the failure mode tested by them. First, the test structures for the analysis of the failures due to the process induced defects are described. Then, the test structures for the analysis of the failures due to traps at the interface silicon-oxide and mobile alcali ions in oxide are discussed. Finally, the test structures for the analysis of the metallization failures are considered.