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At the L/S band, the digital array radars with digital beam-forming characteristics require a compact RF module for a plane array. Such an RF module would require a small-sized local clock generation to synchronize with the central distributed clock signal. This paper proposes a 0.04 mm2, broadband local clock generation for the RF module in digital array radar. In such a multi-band digital array radar, the linearity of the clock generator is a bottleneck. A linearity enhanced algorithm for switched-capacitor digitally-assisted oscillators is proposed in this paper. In this linearity enhancement technique, a calibration resistor array is used to improve frequency-tuning characteristics. The digitally-assisted oscillator has a highly linearized frequency tuning curve without demanding much more power and silicon area. A prototype is fabricated using a 55-nm CMOS process. From measurement, it has a frequency tuning range from 1.3 GHz to 2.5 GHz while occupying 225 × 180 μm2. The measured coarse bank tuning maximum DNL is 0.39 LSB, and the maximum INL is 4.64 LSB, which has been reduced to 43% of the other state-of-art work. The maximum power consumption is 15.8 mW from a 1.2 V supply voltage.

This paper presents design techniques and measurement results of a radiation-hardened mixed-signal microcontroller system-on-chip (SoC) dedicated to fully-customized nanosatellites for the civil active space debris (ADR) cleaning missions. The design requirements are firstly given. The architecture of an on-board computer (OBC) is then described. A radiation-hardened-by-design (RHBD) SoC is proposed for such applications to obtain a long operational period. The proposed SoC is composed of a dual-modular redundant (DMR) 16-bit RISC processor, a 1 kB SRAM, a 12-bit pipelined SAR ADC, a 12-bit current-steering DAC and an on-chip clock generator. The radiation-hardened-by-design techniques are adopted to resist the total-ionization-dose (TID) effects. An SoC prototype is designed and fabricated in 180 nm CMOS process. The electronical performance of devices-under-test (DUTs) has been measured based on a customized mother-daughter board. The performance of the proposed SoC meet the requirements of the nanosatellites. Furthermore, the TID radiation effect experiment is performed. It indicated that the proposed SoC can resist the total dose of more than 300 krad (Si) at the dose rate of 50 rad (Si)/s.

An area efficient, programmable multichannel, multiphase clock generator is proposed to improve the phase resolution for focus ultrasound applications. By using the proposed phase-folding method, the cell amount for generating 360 phases are reduced from 360 to 38 cells. The proposed clock generator is able to provide 360 phases in real-time with 1° phase resolution, 1–51.9% 6-bit DPWM for each channel, and which output frequency varies from 0.1 to 1.5 MHz. Due to the proposed multiphase system is a real-time system, many independent multichannel applications such as focus ultrasound could easily adopt the proposed structure. A new phase-error calibration method for PLL is also present in this paper for reducing the static phase-error due to process voltage and temperature variation. It improves the accuracy of the phase difference in the multiphase system. The proposed ASIC was fabricated in a standard 0.18 μm CMOS process. Measured result shows that multiphase clock generator is able to provide 360 selective phases for each channel. The derived DNL is from −0.106 to +0.108 LSB, and the INL is from −0.284 to +0.449 LSB at 1 MHz.

Charge-redistribution successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used for their simple architecture, inherent low-power consumption and small footprint. Several techniques aiming to reduce the power consumption, to increase the speed, and to reduce the capacitance spread have been developed, such as splitting the digital-to-analog converter (DAC) capacitor array, and charging and discharging the DAC capacitors in multiple steps. In this paper, a fully differential, low-power, passive reference voltage sharing SAR ADC architecture is presented, along with its theoretical analysis and test results. In this architecture, suitable for low sampling rate and low-resolution applications, the reference voltage is scaled down by successively connecting equally sized capacitors in parallel, allowing the use of small capacitor for its implementation. The implemented 6-bit ADC is one of the smallest ADCs reported in a 180-nm technology, and features a FoM between 30.8 and 39.3fJ per conversion step without considering the clock generator power consumption.

In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25µm 60V BCD process. Measurement of 10 dies in the range of 0?C to 100?C is carried out to verify that the worst frequency drifting error is ?3.07%.

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for todayÂ?s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130nm CMOS technology. The measurement results show that the analog front-end has up to 88dB signal-to-noise ratio. And the DSP platform consumes about 0.86mA current at 8MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2mA at 1V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers. The 1.2mA fully integrated SoC for hearing aids.Display Omitted We propose a 1.2mA fully integrated SoC for todayÂ?s digital hearing aids.A flexibility and high power-efficiency DSP platform is developed for audio processing.Acoustic test results show that the SoC is a promising candidate for hearing-aid manufacturers.

In the paper we propose a novel architecture and implementation of 11-bit Digital Pulse WidthModulator (DPWM) circuit based on previously known building blocks. Linearized Class-AD Double-sided (LADD) algorithm has been used to calculate the DPWM signals of the 11-bit resolution hybridDPWM for a Class-AD digital audio amplifier. Noise-shaping process is used to support high fidelity withpractical values of time resolution. The proposed DPWM circuit is composed of 8-bit counter and AnalogDelay Locked Loop (ADLL) using 4-bit tapped delay line. A dual ADLL employing coarse and fineprogrammable delay element is used to adjust the delay time of delay line and lock it to required time.The coarse- as well as fine-delay lines are implemented as a cascade of variable-delay elements based onshunt capacitor delay element or single-ended Schmitt trigger. The proposed 11-bit DPWM circuit, at aswitching frequency of 352.8 kHz and clock generator frequency of 90.3 MHz allows us to attain SNR of120 dB and THD of the output signal less than 0.1% within the audio baseband and modulation indexM¼0.95. Basic verification of circuit manufacturability and simulation results (Monte Carlo analysis) forreal CMOS process are presented.& 2014 Elsevier Ltd. All rights reserved.

This paper presents a multiple frequency clock generator that is composed of the wide operation frequency range phase interpolator and the phase combiner. The wide operation frequency range phase interpolator is developed using a delay-time-adjustment phase interpolator (DTAPI) circuit with various oscillation frequencies for different clock domain applications. The phase combiner generates multiple clock frequencies through various phase combination inputs generated by the preceding proposed phase interpolators. The varying output transition delay time of the proposed DTAPI is the result of the various oscillation frequencies of the voltage-controlled oscillator. The test chip was fabricated in a [email protected] CMOS process with a 1.8V supply voltage. The measured phase noise and power dissipation are -87.28dBc/Hz at 1MHz offset frequency from 88.8MHz and 1.32mW, -77.47dBc/Hz and 2.06mW from 797.8MHz, respectively. The duty cycle error rate of the output clock frequency is less than 1.5%.

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a [email protected] CMOS technology and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is [email protected] at 304MHz.

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm2. With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a [email protected] CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7ps over the operating frequency range of 200MHz-1GHz and the power consumption is 4.8mW at 1GHz. The maximum lock time is 20 clock cycles.

In this paper, a novel spread spectrum clock generator (SSCG) which spreads spectrum with variable current is presented. The proposed SSCG circuit not only occupies a small area but also minimizes effect caused by leakage current. The proposed SSCG circuit has been fabricated in a [email protected] BCD process and applied to a fly-back converter. The effectiveness of the proposed SSCG circuit in terms of peak EMI reduction is demonstrated theoretically and confirmed with experimental results.

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.

This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most eight reference cycles. ASICs in CMOS AMS [email protected] and UMC [email protected] have been manufactured and tested. Measurements show competitive results to state-of-the-art mixed-signal implementations.