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The article presents a hardware and software system used for functional testing of NAND-memory chips based on FPGA. The system's module structure allows simultaneous testing of up to 144 memory chips. The system performs testing according to the predetermined algorithms and allows controlling time characteristics of NAND-memory integrated circuits. The developed software is used to tune and control the process of testing according to the user's needs, and to analyze the obtained data. Validation is performed using a NAND testing commercial system. The results of testing trial batches of multi-chip NAND-memory modules are presented.

This paper proposes a Recurrent Neural Network (RNN) method for modeling transient fault effects on microelectronic devices. RNNs can estimate the impacts of glitches propagated through the circuits, fast and accurately. The estimation phase begins with the learning of behavior of the gates, i.e., NOT, AND, NAND, etc. Then, it provides fast and meticulous evaluations of the transient fault influences on circuits. Simulation results illustrate that the RNN develops the capabilities of conventional methods to explicit forms and impacts of transient faults. The findings accrued from RNN analysis of a 32-bit multiplier, demonstrate 2736x time speed-up with the 4.13 of accuracy loss in contrast with the HSPICE’s simulation time and output values. Additionally, in terms of estimating multiple transient fault effects on the 4-bit Multiply and Accumulate (MAC) circuit, compare to HSPICE’s, there is 16.69x time-acceleration with the 0.048 penalties in output signals’ values. The model considers the triple masking effects, re-convergent fan-out, and fault influences during several clock cycles.

In this paper, two efficient low-cost and high-throughput structures of the SPONGENT lightweight hash function are presented. Two structures are called full data-path width (parallel) and 4-bit serialized. The serialized architecture is designed by using one multi-task shift register in the round computations with minimum hardware resources. The area consumed in this structure is lower than that of the full data-path structure but the number of clock cycles is increased. The speed computation of the full data-path is higher compared to the 4-bit serialized structure of the SPONGENT hash function because the data are computed in a parallel form. To improving the timing characteristics, we implement the S-box block as the complex block in the SPONGENT hash function based on an Area × Delay optimized circuit. A large number of gates, in the structure, have been implemented by 2-input NAND and 2-input NOR gates in order to reduce delay and area. The performance measurement of the proposed structures is performed by evaluating the parameters such as area consumption, computation time, critical path delay (CPD), throughput, and throughput/area. The implementation results are achieved for all variants of the SPONGENT hash function in 180 nm CMOS technology. The results of area consumption (for 4-bit serialized structure) and throughput (for full data-path structure) show improvements compared to previous works. For area-constrained applications, the proposed structure with a lower data-path width is an appropriate choice. The full data-path width structure can be used for the high-speed and high-throughout cryptographic applications.

In the proposed work, we have implemented all logic gates (AND, OR, NOR, NAND, Ex-OR, and Ex-NOR) on a single chip by utilizing the Ti-Diffused lithium niobate (Ti-LiNbO3) based Mach-Zehnder Interferometers. Earlier, many separate photonic devices were developed for individual logic gates. But, proposed gates are highly optimized for high-speed processing combinational circuits by their uniqueness as a single device for all-logic gates. The Beam propagation method (BPM) is acclimated for modeling, study and simulation of the proposed structure. This macrocosmic design can handle immensely colossal combinational circuits with high-speed processing. An insertion loss of 0.83 ​dB and an extinction ratio (ER) of 9.01 ​dB are reported. The simulated results are verified utilizing mathematical computation and MATLAB simulation.

After the development of TLC (Triple level cell) NAND, QLC (Quad level cell) technology will be one of the solutions for next generation NAND flash product. QLC (4 bits/cell) NAND's data levels are up to 16 levels which bring the narrower and tighter voltage ranges and worse performance. This paper studies QLC program and read mechanisms, and presents five types of program algorithms for writing data in QLC cells. Correspondingly, the enhanced Gray coding methods for data mapping based on these different program algorithms are researched. They will be beneficial to data reading. After simulating with changing cell voltages to generate the data errors in the QLC model, the paper presents four enhanced Gray codings to match 16 voltage levels for different program algorithms and read operations. This study will improve the efficiency and keep balance in system-level application for the data error correction of QLC 4 pages which are mapped in the same wordline (WL).

A SPICE macro-model constructed of 3-series-connected-transistors is proposed to describe the IV behavior of a 2-bits/cell split-gate flash memory cell for the first time. The model features 3 different memory states of the cell, namely ‘11′, ‘10′ and ‘01′ at different temperatures (−40 to 125 °C). The cell is constructed of a select-gate transistor in the center with two symmetrical floating gate transistors in two sides. Using the method of capacitive coupling, the model describes the floating gate transistor with BSIM4 (level=54) model with the floating gate voltages changed into a linear combination of the control gate voltage and the select gate voltage. All the BSIM model parameter extraction strategies are applicable for the extraction flow. This novel 2-bits/cell split-gate flash memory cell is fabricated by a 90 nm 4-poly 4-metal CMOS process of Shanghai Huahong Grace Semiconductor Manufacturing Corporation.

This paper presents a modified low-voltage MOS current mode logic (MCML) exclusive-OR (XOR) gate. The proposed topology introduces multiple threshold voltage transistors in the triple-tail cell of a MCML XOR gate. This scheme allows reduction in the implementation area of a triple-tail cell and the logic gate employing it. The impact of employing multiple threshold voltage transistors on the operation of the XOR gate is investigated; and mathematical formulations for the static and delay parameters are derived. A design procedure based on the static model is put forward. The accuracy of the models is verified by designing and simulating the proposed XOR gate for wide operating conditions. The model parameters of TSMC 0.18m CMOS technology are used. An assessment in terms of implementation area and the process variations is conducted for the proposed and the available XOR gates. Finally, the performance of all the XOR topologies is compared for different design cases and the favorable cases are identified.

Accurate analytical timing models are desirable for CMOS logic gates designed using nanometer technology nodes. However, many of them are available for Inverter only and other logic gates are handled by collapsing them into equivalent Inverter. Developing an accurate analytical timing model for combinational logic gates entails the challenge of inclusion of the impact of voltage transition at the intermediate nodes in the series stack of transistors. Therefore, we propose an analytical timing model for 2-input NAND gate based on the relation between the time lag between any two voltage values at the input and output nodes. While deriving our delay model we take into account the nature of voltage transition at the intermediate nodes, input-to-intermediate node capacitive coupling, parasitic capacitance at the intermediate node, and the region of operation of series connected transistors. We explore the region of validity of our derived model in the input signal transition time (TR) and load capacitance (Cl) space. To generalize our model, we relate the model coefficients with the gate size, power supply voltage (Vdd), carrier mobility, threshold voltage, and temperature. While deriving this relation, we also consider the layout dependent effects due to process induced mechanical stress. We observe that the derived models depict an average error of only 0.5% as compared to HSPICE simulation results. To demonstrate the utility of our model, we show that the use of our model reduces the number of SPICE simulations by nearly 80% of that is required for Effective Current Source Model (ECSM) library characterization. Besides this, the presented model can also be used to improve the library characterization process in Dynamic Voltage Frequency Scaling (DVFS) applications.

Resistive switching devices are an emerging class of non-volatile memory elements suited for application in passive nano-crossbar arrays. These devices can be modeled as dynamical systems, i.e. memristive devices or memristors for short. The built-in non-linear switching kinetics of these devices enables the performance of 'stateful' logic operations and widens the applicability of memory arrays towards logic operations. In this work, two logic-in-memories approaches are studied by means of dynamical simulations. The first one is the initial 'stateful' logic concept introduced by Boghetti et al., and the second approach is the complementary switch-based concept later suggested by Linn et al. In both cases, the considered device is an electrochemical metallization cell for which good dynamical models are available. The study is limited to the comparison of elementary logic functions-multi-stage logic as well as parallelization features of both approaches are not considered here. A comparison of the elementary logic IMP and NAND operations in terms of reliability, switching energy and basic array compatibility is conducted, and crucial requirements for both approaches are identified.

This work presents a 4-bit shift-register designed with single-electron tunneling devices. Firstly, a single-electron D flip-flop based on NAND gates was designed and simulated. Based on D flip-flops, the shift-register architecture was also designed and successfully simulated at room temperature. Some considerations about noise margin were made. Moreover, stability analyses for the SET NAND, SET D flip-flop and SET shift-register were carried out.

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I"[email protected]/@mm and V"D"S=0.5V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V"D"D=0.5V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ~20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V"D"D=0.5V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ~10%, ~35% and ~25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.

A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using [email protected] and 90nm CMOS process technologies. The proposed full-adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.

CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide-nitride-oxide-silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density.

A single-electron universal Control–Control-Not gate (CCN gate) is presented in this paper. Bits of information are represented by the presence or absence of single-electrons at conducting islands. The logic operation of the CCN gate as well as its XOR, AND, NAND and NOT operation is verified using simulation. The stability of its universal operation is analysed using a Monte Carlo method. Stability analysis using free energy diagrams and stability plots verify the correct and stable operation of the gate.

A new single-electron circuit implementing the logic function XOR is presented in this paper. The logic gate proposed consists of five tunnel junctions, two capacitors and four islands. The operation of this gate is analysed using Monte Carlo simulation. The simulation results show that the gate operates in stable regions.

The transfer characteristic of CMOS NAND and NOR m-input logic circuits, when the first m-n inputs are passive and remaining n are active is analized in this paper. It is shown that the optimum ratio of constants s of the series and parallel transistors is equal to the number of inputs of a logic circuit. This is valid for any number of active inputs.

Novel CMOS gate circuits are proposed with the regenerative action at one input only. A Schmitt trigger is built in the inside of the conventional NOR or NAND gate instead of a CMOS transistor pair. There is a hysteresis only if the input which appertains to the Schmitt trigger is active. Otherwise, there is no positive feedback and the circuit acts as a conventional NOR or NAND gate.