1. Wafer level Cu–Cu direct bonding for 3D integration.
- Author
-
Kim, Sarah Eunkyung and Kim, Sungdong
- Subjects
- *
SEMICONDUCTOR wafer bonding , *COPPER compounds , *INTEGRATED circuits , *ELECTRIC resistance , *SILICA , *WARPAGE in electronic circuits - Abstract
Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO 2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for electrical resistance distribution. Wafer alignment during stacking process was found to be affected by several factors like non-uniform bump height, the spacers in a bonding fixture and wafer warpage. Step by step warpage measurement revealed that the wafer warpage was dependent on process steps and worsened at bonding step. [ABSTRACT FROM AUTHOR]
- Published
- 2015
- Full Text
- View/download PDF