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The hazards of planetary gearboxes’ failures are the most crucial in the machinery which directly influence human safety like aircrafts. But also in an industry their damages can cause the large economic losses. Planetary gearboxes are used in wind turbines which operate in non-stationary conditions and are exposed to extreme events. Also bucket-wheel excavators are equipped with high-power gearboxes that are exposed to shocks. Continuous monitoring of their condition is crucial in view of early failures, and to ensure safety of exploitation. Artificial neural networks allow for a quick and effective association of the symptoms with the condition of the machine. Extensive research shows that neural networks can be successfully used to recognize gearboxes’ failures; they allow for detection of new failures which were not known at the time of training and can be applied for identification of failures in variable-speed applications. In a majority of the studies conducted so far neural networks were implemented in the software, but for dedicated engineering applications the hardware implementation is being used increasingly, due to high efficiency, flexibility and resistant to harsh environmental conditions. In this paper, a hardware implementation of an artificial neural network designed for condition monitoring of a planetary gearbox is presented. The implementation was done on a Field Programmable Gate Array (FPGA). It is characterized by much higher efficiency and stability than the software one. To assess condition of a gearbox working in non-stationary conditions and for chosen failure modes, a signal pre-processing algorithm based on filtration and estimation of statistics from the vibration signal was used. Additionally, the rewards-punishments training process was improved for a selected neural network, which is based on a Learning Vector Quantization (LVQ) algorithm. Presented classifier can be used as an independent diagnostic system or can be combined with traditional data acquisition systems using FPGAs. [ABSTRACT FROM AUTHOR]

Gearboxes have a significant influence on the durability and reliability of a power transmission system. Currently, extensive research studies are being carried out to increase the reliability of gearboxes working in the energy industry, especially with a focus on planetary gears in wind turbines and bucket wheel excavators. In this paper, a signal pre-processing algorithm designed for condition monitoring of planetary gears working in non-stationary operation is presented. The algorithm is dedicated for hardware implementation on Field Programmable Gate Arrays (FPGAs). The purpose of the algorithm is to estimate the features of a vibration signal that are related to failures, e.g. misalignment and unbalance. These features can serve as the components of an input vector for a neural classifier. The approach proposed here has several important benefits: it is resistant to small speed fluctuations up to 7%, it can be performed in real-time conditions and its implementation does not require many resources of FPGAs. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents FPGA implementations of an adaptive linear neural network (ADALINE) based adaptive filter for power-line noise cancellation in surface Electromyography (sEMG) signals. 10-Tap ADALINE filters in the 16-bit Q0.15 fixed-point format are offered into two categories: small area implementations and high-throughput implementations. The small area ones are optimized by using the resource-sharing technique that considers the interconnect complexity. For the high-throughput ones, we propose the delayed ADALINE (DADALINE) pipelined adaptive filter which is based on the relaxed look-ahead technique. The implementation results on the Xilinx XC3S1200E-4FG320 FPGA show that the smallest implementation achieved the throughput of 1.61million samples per second (MSPS) and the area of three multipliers, 611 LUTs, and 511 flip-flops, and the fastest implementation achieved 56.15 MSPS and the area of 23 multipliers, 945 LUTs, and 907 flip-flops. Each implementation has been tested on an FPGA board interfaced with an sEMG measurement set. [Copyright &y& Elsevier]