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To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2010.04.009 Byline: Luis Morales-Velazquez (a), Rene de Jesus Romero-Troncoso (a)(b), Roque Alfredo Osornio-Rios (a), Gilberto Herrera-Ruiz (a), Eduardo Cabal-Yepez (b) Keywords: Open-architecture; Multi-agent platform; Hardware-software co-design; FPGA; Intelligent manufacturing systems Abstract: New generation of manufacturing systems endows their intelligence and reconfigurability to the computerized numerical controller (CNC) machines. This paper presents an open-architecture platform based on multi-agent hardware-software units, by developing a novel Multi-Agent Distributed CONtroller (MADCON) system. This system intends to fulfill the requirements of reconfigurability for the next generation of intelligent machines. The design of intelligent drives for this system follows a hardware-software co-design approach using a simple and intuitive structure. The hardware units of the proposed system integrate control and monitoring functions providing an FPGA-based open architecture for reconfigurable applications. On the other hand, software components were developed utilizing the XML structure for system description files, gathering features like a flowchart descriptive language and a graphic user-interface. MADCON was applied to a retrofitted to CNC lathe for control and monitoring in order to validate the proposed architecture towards the development of new generation intelligent manufacturing systems. Author Affiliation: (a) Facultad de Ingenieria, Universidad Autonoma de Queretaro, Cerro de las Campanas s/n, 76010 Queretaro, Qro., Mexico (b) Division de Ingenieria - Salamanca, Universidad de Guanajuato, Carr. Salamanca - Valle de Santiago km 3.5+1.8 Com. de Palo Blanco, 36700 Salamanca, Gto., Mexico Article History: Received 26 September 2009; Revised 23 March 2010; Accepted 29 April 2010

• This paper is original given that serve as directive for researchers in the area of FPGA-based deep learning accelerators. • This paper analyzes the characteristics of existing architectures to finally propose the better development strategies. • The literature used in this paper is very recent (many references are in 2018). Deep learning, the fastest growing segment of Artificial Neural Network (ANN), has led to the emergence of many machine learning applications and their implementation across multiple platforms such as CPUs, GPUs and reconfigurable hardware (Field-Programmable Gate Arrays or FPGAs). However, inspired by the structure and function of ANNs, large-scale deep learning topologies require a considerable amount of parallel processing, memory resources, high throughput and significant processing power. Consequently, in the context of real time hardware systems, it is crucial to find the right trade-off between performance, energy efficiency, fast development, and cost. Although limited in size and resources, several approaches have showed that FPGAs provide a good starting point for the development of future deep learning implementation architectures. Through this paper, we briefly review recent work related to the implementation of deep learning algorithms in FPGAs. We will analyze and compare the design requirements and features of existing topologies to finally propose development strategies and implementation architectures for better use of FPGA-based deep learning topologies. In this context, we will examine the frameworks used in these studies, which will allow testing a lot of topologies to finally arrive at the best implementation alternatives in terms of performance and energy efficiency. [ABSTRACT FROM AUTHOR]

Abstract: The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts. [Copyright &y& Elsevier]

Wireless multimedia communication systems become increasingly more computational intensive and demand for higher flexibility. The realization of these systems on reconfigurable hardware offers a good balance for these requirements. In this paper the suitability of commercially available reconfigurable hardware platforms for the target application domain is evaluated. Based on this evaluation a heterogeneous partly reconfigurable system-on-chip platform is identified as ideal implementation platform for the targeted systems. Systems from different target domains are analysed and different cases where the inclusion of reconfigurable hardware in their realizations would lead to improved quality in terms of implementation efficiency and flexibility are identified. Design methodology requirements for the realization of systems from the target application domain on the targeted platform are analysed and issues not covered by existing methodologies are identified. The principles of a methodology handling these open issues are described. Results from the prototyping of different systems are also presented and show the potentials of a reconfigurable hardware platform, which in the future will lead to reduced costs and increased flexibility of the wireless multimedia communication systems. [Copyright &y& Elsevier]

Hardware accelerated inference is a promising solution for exploiting graph convolutional networks (GCN) in latency-sensitive applications. Existing accelerators overlook an important barrier to widespread adoption: the input data (i.e., weighted graphs) of GCN inference diverge from scale and sparsity, causing the accelerators optimized for an array of graphs to lose efficiency on other graphs. This paper presents a reconfigurable GCN inference accelerator, VIDGCN, that switches between all possible GCN inference computation schemes to realize timely inference for all input graphs. VIDGCN incorporates an analytical performance model and a reconfigurable hardware design. The performance model allows users to find the optimal computation scheme for any given input graph. The hardware design reuses all the computation units under all computation schemes, and only distributes the data to the units in different ways. Evaluation on seven real-world graphs shows that VIDGCN outperforms state of the art, SGCNAX, by 1.79 × , and consistently yields the ideal amount of memory accesses. [ABSTRACT FROM AUTHOR]

Semantic trees are a particular type of trees widely used in the representation of the concepts and their relations. Therefore, a computational model of the reality can be built and processed by Artificial Intelligence algorithms to infer knowledge, make decisions, etc. In this work, the design of a hardware component to accelerate reasoning operations on semantic trees by means of an FPGA based platform is presented. The target application is common-sense reasoning where marker-passing algorithms work on semantic tree structures; the core of the Scone Knowledge-Based system. On top of the functionality to be implemented, a strategy to deal with the implementation in reconfigurable hardware of dynamic and recursive data structures has been envisioned. Since lists, graphs or trees are the cornerstone in the modelling of computer friendly solutions for complex problems; this proposal contributes to reduce the breach between the software and silicon domains. As a result, an optimized micro-architecture of an FPGA accelerator for marker-passer algorithms integrated into a heterogeneous computing platform, and a smart data mapping procedure have been delivered. The design has been prototyped on a Xilinx ML507 board and compared to an equivalent software implementation, showing a significant reduction in execution times. [ABSTRACT FROM AUTHOR]

In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. [ABSTRACT FROM AUTHOR]

Abstract: Secure multicast applications of multimedia contents, such as Internet TV, pay per view, satellite TV, etc., need to maintain a high number of keys. In these applications, a user contracts a group of channels or even specific content (films, sports, etc.) which do not have to coincide with the services contracted by other users, so different keys are needed to encrypt the contents. These keys must be recalculated, encrypted and redistributed when a user joins or unjoins a specific group in order to prevent users who do not belong to a group from being able to access the contents. Original algorithms generate only one group key for all users, so this key must be recalculated and resent when a user joins or unjoins in the user group. This is an important problem, because a group key could be changed even when one content is performing. This paper presents a high performance implementation of one of the most employed algorithms of group key maintenance, the LKH algorithm, using reconfigurable hardware and a very high and realistic number of users (8,388,609). The performance obtained by this study improves a lot other results found in the literature in terms of both performance and number of users. [Copyright &y& Elsevier]

Abstract: Power-efficiency has been a key issue for today’s application and system design, ranging from embedded systems to data centers. While application-specific designs and optimizations may improve the power efficiency, it requires significant efforts to co-design the hardware and software, which are difficult to re-use. On the hardware front, the trend of heterogeneous computing enables custom designs for specific applications by integrating different types of processors and reconfigurable hardware to handle compute-intensive tasks. However, what is still missing is an elegant application framework, i.e., a programming environment and a runtime system, to develop portable applications which can offload tasks or be reconfigured dynamically to run on a variety of systems efficiently. Our ongoing work, MobileFBP, provides an application framework which aims to support heterogeneous and reconfigurable systems. Using the framework, the developers build portable applications with a dataflow programming paradigm, and the MobileFBP runtime system dynamically schedules the task components to run on available computing resources locally or remotely based on the application profiles. We hope that this ability produces high-level portable applications and reduces the efforts and skills needed for the developers to optimize their applications on a range of systems. This paper describes this work and presents our preliminary results. [Copyright &y& Elsevier]

Abstract: To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a model-based verification and estimation framework is proposed to make model-driven architecture (MDA) more realistic and applicable to the DPRS design. Considering inherent characteristics of DPRS and real-time system requirements, a semi-automatic model translator converts the UML models of DPRS into timed automata models with transition urgency semantics for model checking. Furthermore, a UML-based hardware/software co-design platform (UCoP) can support the direct interaction between the UML models and the real hardware architecture. Compared to the existing estimation methods, UCoP can provide accurate and efficient platform-specific verification and estimation. We also propose a hierarchical design that consists of a hardware virtualization mechanism for dynamically linking the device nodes, kernel modules, and on-demand reconfigurable hardware functions and a hardware preemption mechanism for further increasing the utilization of hardware resources per unit time. Further, we realize a dynamically partially reconfigurable network security system (DPRNSS) to show the applicability and practicability of the MPC methodology. The DPRNSS cannot only dynamically adapt some of its hardware functions at run-time to meet different system requirements, but also determine which mechanism will be used. Our experiments also demonstrate that the hardware virtualization mechanism can save the overall system execution time up to 12.8% and the hardware preemption mechanism can reduce up to 41.3% of the time required by reconfiguration-based methods. [Copyright &y& Elsevier]

Abstract: A scheme for time and power efficient embedded system design, using hardware and software components, is presented. Our objective is to reduce the execution time and the power consumed by the system, leading to the simultaneous multi-objective minimization of time and power. The goal of suitably partitioning the system into hardware and software components is achieved using Genetic Algorithms (GA). Multiple tests were conducted to confirm the consistency of the results obtained and the versatile nature of the objective functions. An enhanced resource constrained scheduling algorithm is used to determine the system performance. To emulate the characteristics of practical systems, the influence of inter-processor communication is examined. The suitability of introducing a reconfigurable hardware resource over pre-configured hardware is explored for the same objectives. The distinct difference in the task to resource mapping with the variation in design objective is studied. Further, the procedure to allocate optimal number of resources based on the design objective is proposed. The implementation is constrained for power and time individually, with GA being used to arrive at the resource count to suit the objective. The results obtained are compared by varying the time and power constraints. The test environment is developed using randomly generated task graphs. Exhaustive sets of tests are performed on the set design objectives to validate the proposed solution. [Copyright &y& Elsevier]

Abstract: This paper presents a Configurable System-on-Chip (CSoC) architecture that includes programmable and reconfigurable hardware to cope with the flexibility and real-time signal processing demands in future telecommunication and multimedia systems. A programmable micro Task Controller (mTC) with a small instruction set and a novel pipelined configuration technique with descriptors as configuration templates allows a dynamic use of physical processing resources. The CSoC architecture provides a micro-task based programming model, approves a library-based design approach to reduce developing time and costs and allows forward compatibility to other architecture families. It is shown to be easy scalable to future VLSI technologies where over a hundred processing cells on a single chip will be feasible to deal with the inherent dynamics of future applications and system requirements. Several mappings of commonly used signal processing algorithms and implementation results are given for a standard cell ASIC design realization in 0.18μm 6-layer UMC CMOS technology. [Copyright &y& Elsevier]

Reconfigurable architectures combine a programmable–visible interface and the high-level aspects of a computer’s design. The goal of this work is to explore the architectural behaviour of remote reconfigurable systems that are part of general-purpose computers. Our approach analyses various issues arising from the connection of processors with FPGA-based microarchitecture to an existing commodity microprocessor via a standard bus. The quantitative evaluation considers image-processing applications and shows that the maximum performance depends on the amount of data processed by the reconfigurable hardware. Taking images with 256 × 256 pixels, a moderate FPGA capacity of 1E+5 logic blocks provides two orders of magnitude of performance improvement over a Pentium III processor for most of our benchmarks. However, the performance benefits exhibited by reconfigurable architectures may be deeply influenced by some design parameters. This paper studies the impact of hardware capacity, reconfiguration time, memory organisation, and bus bandwidth on the performance achieved by FPGA-based systems. Those image-processing benchmarks that can exhibit high-performance improvement would require about 150 memory banks of 256 bytes each and a bus bandwidth as high as 30 GB/s. This quantitative approach can be applied to the design of high-performance reconfigurable coprocessors for multimedia applications. [Copyright &y& Elsevier]

This work proposes a novel approach to provide comprehensive security to IoT devices. Our approach is based on a reconfigurable hardware-based isolation and protection mechanism (IPM) that operates as a dynamic separation unit between devices and network, far from potential software manipulation. The IPM analyses communications for malicious activities and prevents damage to the IoT device. The IPM leverages a central cloud-based authority to broaden the scope of traffic analysis beyond that of a singular IoT device. The central server evaluates logs from all IPM-protected IoT devices to improve their defense mechanisms and periodically upgrade device IPMs through a remote secure provisioning mechanism. The IPM achieves a 98.68% detection rate when evaluated against a Neptune DoS attack. [ABSTRACT FROM AUTHOR]

Abstract: HPRC (High-Performance Reconfigurable Computing) systems include multicore processors and reconfigurable devices acting as custom coprocessors. Due to economic constraints, the number of reconfigurable devices is usually smaller than the number of processor cores, thus preventing that a 1:1 mapping between cores and coprocessors could be achieved. This paper presents a solution to this problem, based on the virtualization of reconfigurable coprocessors. A Virtual Coprocessor Monitor (VCM) has been devised for the XtremeData XD2000i In-Socket Accelerator, and a thread-safe API is available for user applications to communicate with the VCM. Two reference applications, an IDEA cipher and an Euler CFD solver, have been implemented in order to validate the proposed architecture and execution model. Results show that the benefits arising from coprocessor virtualization outperform its overhead, specially when code has a significant software weight. [Copyright &y& Elsevier]