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Face recognition is used in many applications such as access control, automobile security, criminal identification, immigration, healthcare, cyber security, and so on. Each person has his/her own unique face, so the face can help distinguish people from each other. Feature extraction process plays a fundamental role in accuracy of face recognition, and many algorithms have been presented to extract more informative features from the face image. In this paper, an efficient texture descriptor is proposed based on local information of the face image. In the proposed method, at first, face image is split into several sub-images in such a way that each sub-image includes one of the facial parts such as eyes, nose, and lips. Second, texture features are extracted from each sub-image using a new local pattern descriptor, and then features of sub-images are concatenated to construct feature vector. Finally, the face image is compared to images in a dataset based on a similarity measure. In addition, particle swarm optimization algorithm is used to assign weight to the features of different parts of the face image. To evaluate the proposed algorithm, four face datasets, Yale, ORL, GT and KDEF, are used. Implementation results show that the proposed method outperforms recent methods in terms of accuracy, receiver operating characteristic (ROC) curve, and area under ROC curve. [ABSTRACT FROM AUTHOR]

Two-dimensional convolution plays a fundamental role in different image processing applications. Image convolving with different kernel sizes enriches the overall performance of image processing applications. In this regard, it is necessary to design of reconfigurable convolver with respect to desired kernel sizes list. In this paper, a novel approach is presented for implementation of an area-efficient reconfigurable convolver with appropriate throughput and convolution computational time for an arbitrary kernel size list. This approach is based on the adjustment of logical blocks arrangement in the conventional convolvers. The feasibility and benefits of the proposed approach are demonstrated through a case study of the design implementation on an FPGA platform using the XILINX ISE software. Compared to the well-known reconfigurable convolvers, the proposed design significantly reduces convolution computational time and improves throughput with a reasonable number of hardware resources. For instance, the proposed reconfigurable convolver only requires 0.38 ms to perform a 3 × 3 convolution on a 268 × 460 image with 8-bit pixels and only occupies 455 slices resource of Xilinx Virtex-4 (XC4VLX25) FPGA, in which the throughput of 324 million outputs per second (MOPS) is provided with 81 MHz clock frequency for kernel size of 3 × 3. On average, the MPOS of the proposed approach is approximately improved by 43.13% in relation to the other considered alternatives. Experimental results confirm that the proposed reconfigurable convolver is a very competitive design among the alternative reconfigurable convolvers. [ABSTRACT FROM AUTHOR]