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A. Kireeva et al. contributed another paper in the field of cellular automata: "Parallel simulation of drift-diffusion-recombination by cellular automata and global random walk algorithm". Parallel computing technologies enable the solution of large-scale numerical simulation and data processing problems in science and industry. The previously proposed contention-aware scheduling algorithm is formally described with this model, modifications of the algorithm are proposed: look-ahead technique, chunked data transfers, data caching, and peer-to-peer data transfers. [Extracted from the article]

Mobile cloud computing (MCC) integrates mobile computing and cloud computing aiming to extend the capabilities of mobile devices through offloading techniques. In MCC, many controlled experiments have been performed using mobile applications as benchmarks. Usually, these applications are used to validate proposed algorithms, architectures or frameworks. The task of choosing a specific benchmark to evaluate MCC proposals is difficult because there is no standard applications list. This paper presents a systematic mapping study for benchmarks used in MCC research. Taking 5 months of work, we have read 763 papers from MCC field. We catalogued the applications and characterized them considering three facets: category (e.g., games, imaging tools); evaluated resource (e.g., time, energy); and platform (e.g., Android, iPhone). The mapping study evidences research gaps and research trends. Providing a list of downloadable standardized benchmarks, this work can aid better choices to guide more reliable research studies since the same application could be used for different scientific purposes. [ABSTRACT FROM AUTHOR]

Energy distribution networks represent crucial infrastructures for modern society, and various simulation tools have been widely used by energy suppliers to manage these intricate networks. However, simulation calculations include a large number of fluid control equations, and computational overhead limits the performance of simulation software. This paper proposes a universal parallel simulation framework for energy pipeline networks that takes advantages of data parallelism and computational independence between network elements. A non-pipe model of an energy supply network is optimized, and the input and output of the network model in the proposed framework are modified, which can reduce the development burden during the numerical computations of the pipeline network and weaken the computational correlation between different simulated components. In addition, independent computations can be performed concurrently through periodic data exchange procedures between component instances, improving the parallelism and efficiency of simulation computations. Further, a parallel water pipelines network simulation computing paradigm based on a heterogeneous computer hardware architecture is used to evaluate the proposed framework's performance. A series of tests are conducted to verify the accuracy of the proposed framework, and simulation errors of less than 5% are achieved. The results of multi-threaded simulation experiments have demonstrated the feasibility of the proposed framework in a parallel computing approach. Moreover, an Advanced Micro Devices (AMD) Deep Computing Unit (DCU)-parallel program is implemented into a water supply network simulation system; the computational efficiency of this system is compared with that of its serial counterpart. The experimental results show that the proposed framework is appropriate for high-performance computer architectures, and the 18x speed-up ratio demonstrates that the parallel program based on the proposed universal framework outperforms the serial program. That provides the basis for the application of pipe network simulation on high-performance computers. [ABSTRACT FROM AUTHOR]

In embedded systems such as automotive systems, multi-core processors are expected to improve performance and reduce manufacturing cost by integrating multiple functions on a single chip. However, inter-core interference in shared last-level cache (LLC) results in increased and unpredictable execution times for time-sensitive tasks (TSTs), which have (soft) timing constraints, thereby increasing the deadline miss rates of such systems. In this paper, we propose a time-sensitivity-aware dead block-based shared LLC architecture to mitigate these problems. First, a time-sensitivity indication bit is added to each cache block, which allows the proposed LLC architecture to be aware of instructions/data belonging to TSTs. Second, portions of the LLC space are allocated to general tasks without interfering with TSTs by developing a time-sensitivity-aware dead block-based cache partitioning technique. Third, to reduce the deadline miss rate of TSTs further, we propose a task matching in shared caches and a cache partitioning scheme that considers the memory access characteristics and the time-sensitivity of tasks (TATS). The TATS is combined with our proposed dead block-based scheme. Our evaluation shows that the proposed schemes reduce deadline miss rates of TSTs compared to conventional shared caches. On a dual-core system, compared to a baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, our proposed dead block-based cache partitioning provides 9.3%, 30.5%, and 2.6% lower average deadline miss rates, respectively. On a quad-core system, compared to the baseline, equal partitioning, and state-of-the-art quality-of-service-aware cache partitioning, the combination of our proposed schemes provides 21.2%, 17.7%, and 4.1% lower average deadline miss rates, respectively. [ABSTRACT FROM AUTHOR]

I/O- and data-intensive workloads, as represented by the Grand Challenge problems, multimedia applications, cosmology simulations, climate modeling, and large collaborative visualizations, to name a few, entail innovative approaches to alleviate the I/O (both bandwidth and data access) performance bottlenecks. The advent of low-cost hardware platforms, such as the Beowulf clusters, has opened up numerous possibilities in mass data storage, scalable architectures, and large-scale simulations. The objective of this Special Issue is to discuss problems and solutions, to identify new issues, and to help shape future research and development directions in these areas. From these perspectives, the Special Issue addresses the problems encountered at the hardware, middleware, and application levels, providing conceptual as well as empirical treatments. [ABSTRACT FROM AUTHOR]

With the incoming 5G access networks, it is forecasted that Fog computing (FC) and Internet of Things (IoT) will converge onto the Fog-of-IoT paradigm. Since the FC paradigm spreads, by design, networking and computing resources over the wireless access network, it would enable the support of computing-intensive and delay-sensitive streaming applications under the energy-limited wireless IoT realm. Motivated by this consideration, the goal of this paper is threefold. First, it provides a motivating study the main “killer” application areas envisioned for the considered Fog-of-IoT paradigm. Second, it presents the design of a CoNtainer-based virtualized networked computing architecture. The proposed architecture operates at the Middleware layer and exploits the native capability of the Container Engines, so as to allow the dynamic real-time scaling of the available computing-plus-networking virtualized resources. Third, the paper presents a low-complexity penalty-aware bin packing-type heuristic for the dynamic management of the resulting virtualized computing-plus-networking resources. The proposed heuristic pursues the joint minimization of the networking-plus-computing energy by adaptively scaling up/down the processing speeds of the virtual processors and transport throughputs of the instantiated TCP/IP virtual connections, while guaranteeing hard (i.e., deterministic) upper bounds on the per-task computing-plus-networking delays. Finally, the actual energy performance-versus-implementation complexity trade-off of the proposed resource manager is numerically tested under both wireless static and mobile Fog-of-IoT scenarios and comparisons against the corresponding performances of some state-of-the-art benchmark resource managers and device-to-device edge computing platforms are also carried out. [ABSTRACT FROM AUTHOR]

This paper explores the possibility of efficiently executing a single application using multicores simultaneously with multiple GPU accelerators under a parallel task programming paradigm. In particular, we address the challenge of extending a parallel_for template to allow its exploitation on heterogeneous architectures. Due to the asymmetry of the computing resources, we propose in this work a dynamic scheduling strategy coupled with an adaptive partitioning scheme that resizes chunks to prevent underutilization and load imbalance of CPUs and GPUs. In this paper we also address the problem of the underutilization of the CPU core where a host thread operates. To solve it, we propose two different approaches: (1) a collaborative host thread strategy, in which the host thread, instead of busy-waiting for the GPU to complete, it carries out useful chunk processing; and (2) a host thread blocking strategy combined with oversubscription, that delegates on the OS the duty of scheduling threads to available CPU cores in order to guarantee that all cores are doing useful work. Using two benchmarks we evaluate the overhead introduced by our scheduling and partitioning algorithms, finding that it is negligible. We also evaluate the efficiency of the strategies proposed finding that allowing oversubscription controlled by the OS can be beneficial under certain scenarios. [ABSTRACT FROM AUTHOR]

Nowadays, multi-core processor is the main technology used in desktop PCs, laptop computers and mobile hardware platforms. As the number of cores on a chip keeps increasing, it adds up the complexity and impacts more on both power and performance of a processor. In multi-processors, the number of cores and various parameters, such as issue-width, number of instructions and execution time, are key design factors to balance the amount of thread-level parallelism and instruction-level parallelism. In this paper, we perform a comprehensive simulation study that aims to find the optimum number of processor cores in desktop/laptop computing processor models with shallow pipeline depth. This paper also explores the trade-off between the number of cores and different parameters used in multi-processors in terms of power-performance gains and analyzes the impact of 3D stacking on the design of simultaneous multi-threading and chip multiprocessing. Our analysis shows that the optimum number of cores varies with different classes of workloads, namely: SPEC2000, SPEC2006 and MiBench. Simulation study is presented using architectures with shorter pipeline depth, showing that (1) the optimum number of cores for power-performance is 8, (2) the optimum number of threads in the range [2, 4], and (3) for beyond 32 cores, multi-core processors are no longer efficient in terms of performance benefits and overall power consumption. [ABSTRACT FROM AUTHOR]

Traversal is a fundamental procedure in most parallel graph algorithms. To explore the massive fine-grained parallelism in graph traversal, the fine-grained data synchronization is critical. On commodity multi-core processors, the widely adopted solution is fine-grained locks (i.e., one lock per vertex). However, in emerging graph analytics of massive irregular graphs (e.g., social network and web graph), it suffers huge memory cost and poor locality due to the large-scale vertex set and inherent random vertex access. In this paper, we propose a novel fine-grained lock mechanism-lock virtualization ( vLock). The key idea is to map the huge logical lock space to a small fixed physical lock space that can reside in cache during runtime. The virtualization mechanism effectively reduces lock incurred extra memory cost and cache misses with only a slight increase of lock conflict rate, while it preserves high portability for legacy codes by providing Pthreads-like application programming interface. Our further analysis reveals that given the random access pattern, the lock conflict rate is no longer related to the size of vertex set but only the numbers of both physical locks and parallel threads, thus vLock is independent from graph topologies. This paper presents a complete description of the vLock method as well as its theoretic foundation. We implemented an vLock library and evaluated its performance in four classic graph traversal algorithms (BFS, SSSP, CC, PageRank). Experiments on the Intel Xeon E5 eight-core processor show that, compared to Pthreads fine-grained locks, vLock significantly reduces lock's cache misses and achieves 4-20 % performance improvement. [ABSTRACT FROM AUTHOR]

With the trend of growing number of integrated processing cores on Chip Multiprocessors, researchers are working hard to increase the available parallelism of software programs so as to efficiently harness the growing computing power. One noticeable direction among these efforts is speculative multi-threading (SpMT), a.k.a thread level speculation, which aims to extract thread level parallelism by splitting a sequential execution thread into several finer ones and execute them on parallel. A SpMT thread is in speculative status before it 'knows' all its input data are correct. A speculative thread needs to write to the L1 cache, but its output might be discarded if the speculation eventually fails. However, another speculative thread may have already read in such speculative output. Therefore, some mechanism is needed to support speculative read and write. And because the SpMT threads are extracted from a single thread, they usually share lots of data, thus there might be intense data coherence among the L1 caches. It would be very complicated to support data coherence and speculation together. This Paper proposes a shared write buffer among the SpMT cores. We are able to confine the speculative read and write in the SWB, thus the speculation will not interference with coherence, and the L1 cache design could be drastically simplified. Experiments show that the SWB can capture a big portion of inter-core data sharing, reduce cache coherence, and drastically improve data access performance of SpMT threads. [ABSTRACT FROM AUTHOR]

Dragonfly networks arrange network routers in a two-level hierarchy, providing a competitive cost-performance solution for large systems. Non-minimal adaptive routing (adaptive misrouting) is employed to fully exploit the path diversity and increase the performance under adversarial traffic patterns. Network fairness issues arise in the dragonfly for several combinations of traffic pattern, global misrouting and traffic prioritization policy. Such unfairness prevents a balanced use of the resources across the network nodes and degrades severely the performance of any application running on an affected node. This paper reviews the main causes behind network unfairness in dragonflies, including a new adversarial traffic pattern which can easily occur in actual systems and congests all the global output links of a single router. A solution for the observed unfairness is evaluated using age-based arbitration. Results show that age-based arbitration mitigates fairness issues, especially when using in-transit adaptive routing. However, when using source adaptive routing, the saturation of the new traffic pattern interferes with the mechanisms employed to detect remote congestion, and the problem grows with the network size. This makes source adaptive routing in dragonflies based on remote notifications prone to reduced performance, even when using age-based arbitration. [ABSTRACT FROM AUTHOR]

With the emergence of high-performance data analytics, the Hadoop platform is being increasingly used to process data stored on high-performance computing clusters. While there is immense scope for improving the performance of Hadoop MapReduce (including the network-intensive shuffle phase) over these modern clusters, that are equipped with high-speed interconnects such as InfiniBand and 10/40 GigE, and storage systems such as SSDs and Lustre, it is essential to study the MapReduce component in an isolated manner. In this paper, we study popular MapReduce workloads, obtained from well-accepted, comprehensive benchmark suites, to identify common shuffle data distribution patterns. We determine different environmental and workload-specific factors that affect the performance of the MapReduce job. Based on these characterization studies, we propose a micro-benchmark suite that can be used to evaluate the performance of stand-alone Hadoop MapReduce, and demonstrate its ease-of-use with different networks/protocols, Hadoop distributions, and storage architectures. Performance evaluations with our proposed micro-benchmarks show that stand-alone Hadoop MapReduce over IPoIB performs better than 10 GigE by about 13-15 %, and the RDMA-enhanced hybrid MapReduce design can achieve up to 43 % performance improvement over default Hadoop MapReduce over IPoIB, in both shared-nothing and shared storage architectures. [ABSTRACT FROM AUTHOR]

Virtual Organizations (VOs) are dynamic collections of individuals, institutions, and resources. VOs are widely accepted in grid and other distributed computing environments. Previous VO research produces several separate tools to provide part of the functionality including user registration, user mapping, authentication, authorization, and VO management. However, none of the work covers all the functionality or focuses on non-functional properties. This paper formally defines virtual organization in terms of three functional requirements and four non-functional properties. The functional requirements are user management, resource management, and VO management. The non-functional properties are decentralization, flexibility, simplicity, and efficiency. The problem is formulated as designing a VO architecture to satisfy the functional requirements and achieve the non-functional properties at the same time. This paper presents a layered architecture with GNode abstraction to construct Agora, an implementation of VOs. In Agora architecture, all the entities including users, resources, and agoras are abstracted as GNodes. A naming layer is constructed to manage these GNodes. At the top, there is a logic layer implementing all Agora functionality based on GNode and managing the physical layer resources. The Agora architecture has been implemented in the Vega Grid Operating System. Agora is deployed in the China National Grid and other grid platforms with more than 27 sites and 19 applications. The evaluations through real applications, high performance computing VO scenarios, and micro benchmarks show that the Agora architecture provides complete VO functionality, while achieving decentralization, flexibility, simplicity, and efficiency. [ABSTRACT FROM AUTHOR]

Today's state-of-the-art Big data analytics engines handle masses of data, but will reach to their limits, as the future Big data flood is predicted to still grow with an increasing speed. Hence we need to think about the next development phase and future features of Big data analytics engines. In this paper, we discuss possible future enhancements in the area of Big data analytics with focus on emergent models, frameworks, and hardware technologies. We point out a selection of new challenges and open research questions. [ABSTRACT FROM AUTHOR]

This paper presents an interconnected distributed architecture for storing data and metadata in large-scale cloud storage systems. The primary goal of the proposed architecture is to enhance the scalability of namespace directory in large-scale file systems. Structural shift from distinguished distributed model to interconnected distributed model and conducting effective coordination among file servers for namespace management are two key solutions considered in the context of proposed architecture. To this intent, a coordination protocol is designed for communication among file servers, and maintaining user transparency in the presence of different file system actions/reactions. The experimental results, obtained via emulations under different network conditions and cloud storage sizes, show up to 43.9% availability and 37.8% connection throughput improvements with negligible storage overhead compared to the latest released version of Hadoop distributed file system. [ABSTRACT FROM AUTHOR]

In this paper, we developed a framework for efficient resource management within the grid service environment. For considering the grid service architecture and functions, the resource management is the most important to grid service; therefore, GridRMF (Grid Resource Management Framework) is modeled and developed in order to respond to such variable characteristics of resources as accordingly as possible. GridRMF uses the participation level of grid resource as a basis of its hierarchical management. This hierarchical management divides managing domains into two parts: VMS (Virtual Organization Management System) for virtual organization management and RMS (Resource Management System) for metadata management. VMS mediates resources according to optimal virtual organization selection mechanism, and responds to malfunctions of the virtual organization by LRM (Local Resource Manager) automatic recovery mechanism. RMS, on the other hand, responds to load balance and fault by applying resource status monitoring information into adaptive performance-based task allocation algorithm. [ABSTRACT FROM AUTHOR]

This paper meets the challenge of harnessing the heterogeneous communication architecture of ccNUMA multiprocessors for heterogeneous stencil computations, an important example of which is the Multidimensional Positive Definite Advection Transport Algorithm (MPDATA). We propose a method for optimization of parallel implementation of heterogeneous stencil computations that is a combination of the islands-of-core strategy and ( 3 + 1 )D decomposition. The method allows a flexible management of the trade-off between computation and communication costs in accordance with features of modern ccNUMA architectures. Its efficiency is demonstrated for the implementation of MPDATA on the SGI UV 2000 and UV 3000 servers, as well as for 2- and 4-socket ccNUMA platforms based on various Intel CPU architectures, including Skylake, Broadwell, and Haswell. [ABSTRACT FROM AUTHOR]

There is rapidly increasing interest in Location Based Service (LBS) which utilizes location data of moving objects. To efficiently manage the huge amounts of location data in LBS, the GALIS (Gracefully Aging Location Information System) architecture, a cluster-based distributed computing architecture, is proposed. The GALIS using the non-uniform 2-level grid algorithm performs load balancing and indexing for nodes. However, the non-uniform 2-level grid algorithm has a problem creating unnecessary nodes when moving objects are crowded in a certain region. Therefore, a new node split algorithm, which is more efficient for various distribution of moving objects, is proposed in this paper. Because the algorithm proposed in this paper considers spatial distribution for the current location of moving objects, it can perform efficient load balancing without creating unnecessary nodes even when moving objects are congested in a certain region. Besides, the various data distribution configuration for moving objects has been experimented by implementing node split simulators and it’s been verified that the proposed algorithm can split nodes more efficiently than the existing algorithm. [ABSTRACT FROM AUTHOR]

Value prediction, a technique to break data dependency, is important in enhancing instruction-level parallelism and processor performance. A new value predictor utilizing both the loop and locality properties of data values has been proposed in this paper to pursue desirable prediction accuracy at reasonable cost. The proposed value predictor, called the Dynamic Loop and Locality-based (DLL) predictor, makes predictions by dynamically practicing the loop or locality-based prediction policy according to the state. With certain simple designs, the DLL predictor gains prediction accuracy in an efficient way. To secure more comprehensive experimental evaluation of value predictors, a new performance measure, accuracy improvement per cost, briefed as the A/C ratio, is introduced in the paper. Simulation results show that, compared with other existing value predictors, the proposed DLL predictor produces better A/C ratios in almost all situations due to flexible application of different prediction policies and reduced cost. [ABSTRACT FROM AUTHOR]

This paper considers a multicore system, equipped with dynamic voltage/frequency scaling (DVFS), which runs real-time jobs with probabilistic characteristics. The DVFS policy directly affects the performance of this system as well as its power consumption through impacting both dynamic and leakage powers. While power consumption determines the processor thermal behavior, the temperature in turn affects the processor power consumption by impacting the leakage power. Additionally, temperature variation of a core is coupled with the thermal behaviors of the other cores, namely thermal effects of the surrounding components. These inter-effects make sophisticated relations between the nature of the stochastic real-time system and its performance, power consumption, and temperature behavior. In this paper, we first present an exact thermal analysis approach for the specified system considering these inter-effects. We then propose a scalable approximate method for thermal analysis of the system based on the exact analysis. The proposed analytical method outperforms the traditional simulation-based methods in terms of time complexity, by approximately three orders of magnitude, while introducing a relative error of less than 0.8 % for the mentioned setups. Also, we show the efficacy of the proposed analytical method in temperature-aware power minimization, resulting in significant reductions in the system-wide power consumption. [ABSTRACT FROM AUTHOR]

Time series analysis is an important research topic of great interest in many fields. Recently, the Matrix Profile method, and particularly one of its implementations—the SCRIMP algorithm—has become a state-of-the-art approach in this field. This is a technique that brings the possibility of obtaining exact motifs from a time series, which can be used to infer events, predict outcomes, detect anomalies and more. However, the memory-bound nature of the SCRIMP algorithm limits the execution performance in some processor architectures. In this paper, we analyze the SCRIMP algorithm from the performance viewpoint in the context of the Intel Xeon Phi Knights Landing architecture (KNL), which integrates high-bandwidth memory (HBM) modules, and we combine several techniques aimed at exploiting the potential of this architecture. On the one hand, we exploit the multi-threading and vector capabilities of the architecture. On the other hand, we explore how to allocate data in order to take advantage of the available hybrid memory architecture that conjugates both the high-bandwidth 3D-stacked HBM and the DDR4 memory modules. The experimental evaluation shows a performance improvement up to 190 × with respect to the sequential execution and that the use of the HBM memory improves performance in a factor up to 5 × with respect to the DDR4 memory. [ABSTRACT FROM AUTHOR]

In this era of big data, as the data size is scaling up, the need for computing power is exponentially increasing. However, most of the community detection algorithms in the literature are classified as global algorithms, which require access to the entire information of the network. These algorithms designed to work on a single machine cannot be directly parallelized. Hence, it is impossible for such algorithms working in stand-alone machines to find communities in large-scale networks and also the required processing power far exceeds the processing capabilities of single machines. In this paper, a set of novel Decentralized Iterative Community Clustering Approaches to extract an efficient community structure for large networks are proposed and devalued using the LFR benchmark model. The approaches have the ability to identify the community clusters from the entire network without global knowledge of the network topology and will work with a range of computer architecture platforms (e.g., cluster of PCs, multi-core distributed memory servers, GPUs). Detecting and characterizing such community structures is one of the fundamental topics in network systems' analysis, and it has many important applications in different branches of science including computer science, physics, mathematics and biology ranging from visualization, exploratory and data mining to building prediction models. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel directory architecture that can dynamically allocate a directory entry for a cache block on demand at runtime only when the block is shared by more than a single core. Thus, we do not maintain coherence for private blocks, substantially reducing the number of directory entries. Even for shared blocks, we allocate directory entry dynamically only when the block is actively shared, further reducing the number of directory entries at runtime. For this, we propose a new directory architecture called dynamic directory table (DDT), which is a decoupled directory storage from the shared cache and dynamically maintains directory entries only for actively shared blocks. Also, we add a small additional victim cache to its original DDT in order to reduce invalidation broadcasts caused by DDT eviction. Through our detailed simulation on PARSEC benchmarks, we show that DDT can outperform the expensive full-map directory by a slight margin with only 16.09% of directory area across a variety of different workloads. This is achieved by its faster access and high hit rates in the small directory. In addition, we demonstrate that even smaller DDTs can give comparable or higher performance compared to recent directory optimization schemes such as SPACE and DGD with considerably less area. [ABSTRACT FROM AUTHOR]

As a variant of the well-known hypercube, the balanced hypercube BHn was proposed as a desired interconnection network topology for parallel computing. It is known that BHn is bipartite. Assume that S={s1,s2} and T={t1,t2} are any two sets of vertices in different partite sets of BHn (n≥1). It has been proved that there exist two vertex-disjoint s1,t1-path and s2,t2-path of BHn covering all vertices of BHn. In this paper, we prove that there always exist two vertex-disjoint s1,t1-path and s2,t2-path covering all vertices of BHn (n≥2) with at most 2n-3 faulty edges. The upper bound 2n-3 of edge faults can be tolerated is optimal. [ABSTRACT FROM AUTHOR]

The use of high-performance computing systems to help to make the right investment decisions in financial markets is an open research field where multiple efforts have being carried out during the past few years. Specifically, the Heath-Jarrow-Morton (HJM) model has a number of features that make it well suited for implementation on massively parallel architectures. This paper presents a multi-CPU and multi-GPU implementation of the HJM model that improves both the performance and energy efficiency. The experimental results reveal that the proposed architectures achieve excellent performance improvements, as well as optimize the energy efficiency and the cost/performance ratio. [ABSTRACT FROM AUTHOR]

In recent years, the sport of mountaineering has become increasingly popular in many countries. Notably, during this activity, mountaineers are likely to enter into dangerous situations. In this paper, we propose a cloud-computing-based architecture to respond rapidly to an SOS emergency event requiring first aid. Our scheme constructs an aid platform based on cloud computing and, on the basis of the features of mobile devices, such as mobility and convenient communication, the injured party/patient can quickly send an SOS and summon aid. In this paper, we propose a scheme with which to accomplish the proxy authorization of the Schnorr signature from the patient. However, security is a very important issue as regards the communication. If an application suffers from a security challenge, the application is not practical. Therefore, the proposed scheme also integrates symmetric encryption technology, a message authentication code and RFC 2631 to defend against known attacks as well as performing an analysis with regards to achieving these security requirements provided by a proxy signature. Finally, we analyze the performance cost to determine whether our scheme is suitable for implementation in an emergency response and SOS system. [ABSTRACT FROM AUTHOR]

Virtual machine (VM) consolidation in Cloud computing provides a great opportunity for energy saving. However, the obligation of providing suitable quality of service to end users leads to the necessity in dealing with energy-performance tradeoff. In this paper, we propose a redesigned energy-aware heuristic framework for VM consolidation to achieve a better energy-performance tradeoff. There are two main contributions in the framework: (1) establish a service level agreement (SLA) violation decision algorithm to decide whether a host is overload with SLA violation; (2) minimum power and maximum utilization policy is then proposed to improve the Minimum Power policy in previous work. Finally, we have evaluated our framework through simulation on large-scale experiments driven by workload traces from more than a thousand VMs, and the results show that our framework outperforms previous work. Specifically, it guarantees 21-34 % decrease in energy consumption, 84-92 % decrease in SLA violation, 87-94 % decrease in energy-performance metric, and 63 % decrease in execution time. And we further discuss why the redesigned framework outperforms the previous design. [ABSTRACT FROM AUTHOR]

For heterogeneous distributed computing systems, important design issues are scalability and system optimization. Given such systems, it is crucial to develop low computational complexity algorithms to schedule tasks in a manner that exploits the heterogeneity of the resources and applications. In this paper, we report and evaluate three scalable, and fast scheduling heuristics for highly heterogeneous distributed computing systems. We conduct a comprehensive performance evaluation study using simulation. The benchmarking outlines the performance of the schedulers, representing scalability, makespan, flowtime, computational complexity, and memory utilization. The set of experimental results shows that our heuristics perform as good as the traditional approaches, for makespan and flowtime, while featuring lower complexity, lower running time, and lower used memory. The experimental results also detail the various scenarios under which certain algorithms excel and fail. [ABSTRACT FROM AUTHOR]

The high density, low power consumption non-volatile memory (NVM) provides a promising DRAM alternative for the in-memory big-data processing applications, e.g., Spark, It is significant to simulate the behaviors when NVMs are deployed into the area of big-data processing before their widespread use in market. However, existing simulation approaches are not applicable for big-data processing due to two reasons. First, some approaches require complicated hardware and/or OS supports. Second, cycle-level or function-level simulations are too time-consuming to simulate the whole software stack of big-data processing. Therefore, the complexity and expensive time cost in NVM simulation have dramatically dragged down the integrated research of big data with NVM. This paper proposes a fast and reconfigurable simulation method, called NVM Streaker, which does not need complex hardware or OS supports. It simulates NVM access costs using disturbed DRAM accesses and commonly configurable hardware parameters. It is fast since we use DRAM accesses and change its access costs to simulate NVM access costs, thus enabling to simulate the whole software stack to run Spark applications. It is reconfigurable since we enable users to configure the disturbed memory access costs, in order to simulate different NVM access costs. The experimental results show that we can simulate Spark applications with almost negligible cost and high efficiency. [ABSTRACT FROM AUTHOR]

In this paper, we proposed an secure IoT framework to ensure an End-To-End security from an IoT application to IoT devices. The proposed IoT framework consists of the IoT application, an IoT broker and the IoT devices. The IoT devices can be deployed along a board line or a boundary of the area of IoT broker. The IoT broker manages their own devices and aggregates their sensing data. The IoT application provides users with IoT services. To use the IoT services, it needs to access to sensing data. Especially, the case of real-time healthcare services should consider intermediate security issues because medical information of patients is one of very sensitive privacy information. However, most of IoT protocols such as CoAP and MQTT have no concern about the End-To-End security, they only depended on the security of DTLS. Therefore, we proposed a new IoT framework to satisfy the End-To-End security feature under the CoAP communication. The proposed framework encrypts sensitive data by a symmetric encryption and an attribute-based encryption for efficiencies of communication and computation costs. In addition, each IoT device has a unique identification used as one of their attributes. Consequently, although the IoT broker is one of the intermediate nodes, it decrypts and shows data only if it satisfies all attributes. [ABSTRACT FROM AUTHOR]

The rapid advancement in communication technologies enables remote users to acquire a number of online services. All such online services are provided remotely facilitating the users to freely move any where with out disruption of the services. In order to ensure seamless and secure services to the remote user such services espouse authentication protocols. A number of authentication protocols are readily available to achieve security and privacy in remote client server architecture. Most of these schemes are tailored for single server architecture. In such scenario, if a user wants to attain the services provided by more than one servers he has to register with each server. In recent times, multiserver authentication has got much attention, where a user can register once and then can acquire services provided by multiple servers. Very recently, Lu et al. proposed a biometric, smart card and password-based three factor authentication scheme usable for multiserver environments. Furthermore, Lu et al. identified their scheme to resist known attacks. However, the analysis in this paper ascertains that Lu et al.’s scheme is vulnerable to impersonation attack. An adversary registered to the system just after knowing the public identity of a user can impersonate himself as the latter. Then we propose an improvement over Lu et al.’s scheme. Our improvement is more robust than the existing schemes. The security of proposed scheme is substantiated formally along with informal security discussion, while same is also validated using a popular automated tool ProVerif. The analysis confirms that proposed scheme achieves mutual authentication and is robust against known attacks. In addition, the proposed scheme does not incur any extra computation as compared with Lu et al.’s scheme. [ABSTRACT FROM AUTHOR]

The rapid increase in performance, programmability, and availability of graphics processing units (GPUs) has made them a compelling platform for computationally demanding tasks in a wide variety of application domains. One of these is real-time computational fluid dynamics, which are computationally expensive due to a large number of grid points that require calculations. One commonly used tool to simulate fluid flows is the Lattice Boltzmann method (LBM), mainly due to its simpler formulation when compared to solving the Navier-Stokes equations, and because of its scalability on parallel processing systems. In this paper, we give an up-to-date survey on the research regarding the LBM for fluid simulation using GPUs. We discuss how the method was implemented with different GPU architectures and software frameworks, focusing on optimization techniques and their performance. Additionally, we mention some applications of the method in different areas of study. [ABSTRACT FROM AUTHOR]

Cloud computing plays a significant role to store and analyze the exponentially growing volume of generated data. However, cloud computing is inherently a frequent environment for failures and its services undergo long downtime periods. These failures threaten the user experience especially when we take into consideration that not only the currently generated data have a tremendous volume but also it presents new types and different generation velocities. Therefore, the aim of this paper is to propose a broker architecture, which ensures that behavioral requirements in terms of dependability properties are met by the provided cloud service at the infrastructure, platform and service levels. This architecture takes the decision to continue the service delivery with the same cloud provider or to migrate toward a new provider based on the evaluation of the fault severity impact. DBA takes into consideration the interdependence between the cloud service models and formalizes all dependability attributes with a single state-based stochastic model. Results demonstrate the introduced amelioration in terms of dependability properties compared to classic cloud service delivery. The main contribution concerns safety improvement by avoiding catastrophic failures. [ABSTRACT FROM AUTHOR]

Internet of things (IoT) has become one of the most important fields in computing arena. The environments of IoT require highly efficient, immediate and worldwide communication services. Accordingly, efficient multicast routing architecture is a fundamental premise for IoT. This paper proposes a mixed multicast architecture for IoT environments that employs the centric, hierarchical, and distributed traditional multicast architectures. The aim is to determine the most suitable traditional multicast architecture, relative to the current state of the IoT system. First, an algorithm to manage the proposed multicast architecture is introduced. Then, an IoT case study for each traditional multicast architecture is demonstrated. Finally, a simulation environment is established, using the network simulator package NS2, to measure the performance of the proposed architecture. The considered performance metrics are end-to-end delay, packet loss, throughput, energy consumption, and transformation rate between traditional multicast architectures. The results demonstrate the superiority of the proposed architecture relative to individual traditional multicast architectures. [ABSTRACT FROM AUTHOR]

Space-time adaptive processing (STAP) has an enormous computational complexity which has confined its practical applications. In this paper, we present an implementation based on field programmable gate array (FPGA) for the most computationally intensive portion of STAP, which is the adaptive weights calculation. This involves solving a set of linear equations that uses the radar return data. In the proposed architecture, QR decomposition block is the most computationally part which is parameterized by vector size to create a trade-off between the hardware resources consumption and delay. To achieve an efficient and high-speed structure, the architecture is simulated and implemented in two cases: single-vector and multi-vector. Results show that the calculation time of weights in single-vector design is less than that of multi-vector case. The delay of weights for 6 × 8 × 120 data cube using vector size of 17 and the maximum clock frequency of 259 MHz is 139 μs, and GFLOPs/Watt is 3.89 for implementation on Arria 10 floating point FPGA. Therefore, the presented approach can realize the real-time requirement and floating point computation of the adaptive weights for STAP. [ABSTRACT FROM AUTHOR]

Lee’s algorithm solves the path-connection problems that arise in logical drawing, wiring diagramming or optimal route finding. Its parallel version has been widely used as a benchmark to test transactional memory systems. It exhibits transactions of large size and duration that stress these systems exposing their limitations. In fact, Lee’s algorithm has been proved to perform similar to sequential in commercial hardware transactional memory systems due to persistent capacity overflows. In this paper, we propose a novel approach to Lee’s algorithm in the context of commercial hardware transactional memory systems. We show how the majority of the computation of the largest transaction, i.e. grid privatization and path calculation, can be executed out of the boundaries of the transaction, thus reducing the size requirements. We leverage the correctness criteria of lazy subscription fallback locks to ensure a correct execution. This novel approach uses transactional memory extensions from commercial processors from a different point of view, not needing either early release or open-nested transaction features that are not yet implemented in these systems. We propose an application programming interface to facilitate the task of the programmer. Experiments are carried out with the Intel Core and IBM Power8 architectures, showing speedups around 3.5× over both the standard transactional version of the algorithm and the sequential for certain grid inputs and four threads. We also compare our proposal with a software transactional memory LeeTM approach. [ABSTRACT FROM AUTHOR]

The increasing data demands of applications from various domains and the decreasing relative power cost of CPU computation have gradually exposed data movement cost as the prominent factor of energy consumption in computing systems. The traditional organization of the computer system software into a layered stack, while providing a straightforward modularity, poses a significant challenge for the global optimization of data movement in particular and, thus, the energy efficiency in general. Optimizing the energy efficiency of data movement in large-scale systems is a difficult tasks because it depends on a complex interplay of various factors at different system layers. In this work, we address the challenge of optimizing the data movement of the storage I/O stack in a holistic manner. Our approach consists of a model-based system driver that obtains the current I/O power regime and adapts the CPU frequency level according to this information. On the one hand, for simplifying the understanding of the relation between data movement and energy efficiency, this paper proposes novel energy prediction models for data movement based on series of runtime metrics from several I/O stack layers. We provide an in-depth study of the energy consumption in the data path, including the identification and analysis of power and performance regimes that synthesize the energy consumption patterns in a cross-layer approach. On the other hand, we propose and prototype a kernel driver that exploits data movement awareness for improving the current CPU-centric energy management. [ABSTRACT FROM AUTHOR]

Current parallel systems composed of mixed multi/manycore systems and/with GPUs become more complex due to their heterogeneous nature. The programmability barrier inherent to parallel systems increases almost with each new architecture delivery. The development of libraries, languages, and tools that allow an easy and efficient use in this new scenario is mandatory. Among the proposals found to broach this problem, skeletal programming appeared as a natural alternative to easy the programmability of parallel systems in general, but also the GPU programming in particular. In this paper, we develop a programming skeleton for Dynamic Programming on MultiGPU systems. The skeleton, implemented in CUDA, allows the user to execute parallel codes for MultiGPU just by providing sequential C++ specifications of her problems. The performance and easy of use of this skeleton has been tested on several optimization problems. The experimental results obtained over a cluster of Nvidia Fermi prove the advantages of the approach. [ABSTRACT FROM AUTHOR]

A new state space representation for a class of combinatorial optimization problems, related to minimal Hamiltonian cycles, enables efficient implementation of exhaustive search for the minimal cycle in optimization problems with a relatively small number of vertices and heuristic search for problems with large number of vertices. This paper surveys structures for representing Hamiltonian cycles, the use of these structures in heuristic optimization techniques, and efficient mapping of these structures along with respective operators to a newly proposed electrooptical vector by matrix multiplication (VMM) architecture. Record keeping mechanisms are used to improve solution quality and execution time of these heuristics using the VMM. Finally, the utility of a low-power VMM based implementation is evaluated. [ABSTRACT FROM AUTHOR]

Dynamic Binary Translation (DBT) has been widely utilized to convert binary code for one Instruction Set Architecture (ISA) to another at run-time and optimize the code when necessary. A two-stage strategy often applies to DBT, which handles hot code and cold code separately using translation and interpretation respectively to ensure execution efficiency. However, an excessively high overhead of interpretation remains to be tackled. It has been observed that interpretation usually involves a large number of redundant redecoding operations. This paper introduces an approach, namely Decoded Instruction Cache (DICache), which caches the information of the interpreted instructions in the history and attempts to reuse the information as much as possible in the future. Performance benchmark has been carried out with the software and the hardware implementations of DICache. The experimental results indicate that DICache can significantly remove the redundancy of redecoding operations, and this results in a dramatic decline of interpretation overhead. [ABSTRACT FROM AUTHOR]

The design trend of high-speed microprocessors is toward wider and wider issue architecture to increase instruction-level parallelism. Such architecture needs a large register file to reduce register pressure. A large register file, however, consumes much more power during program execution. In this paper, we first analyze the register requirements in general programs, especially among those parts of the program which take most of execution time. Next, we drive a power-aware register assignment algorithm to distribute different access-frequencies temporary values over different register groups. Finally, we design a dynamic voltage scaling circuit to save the power consumption for those infrequently accessed registers. Experimental results show that partitioning the storage locations of temporary values in a register file will indeed impact the utilization of each register, and within a DVS approach a large register file can thus save a significant ratio of power consumption. [ABSTRACT FROM AUTHOR]

Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications' needs through hardware reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal cluster size of the architecture. [ABSTRACT FROM AUTHOR]

We present and compare a variety of parallelization approaches for a real-world case study on modern parallel and distributed computer architectures. Our case study is a production-quality, time-intensive algorithm for medical image reconstruction used in computer tomography (PET). We parallelize this algorithm for the main kinds of contemporary parallel architectures: shared-memory multiprocessors, distributed-memory clusters, graphics processing units (GPU) using the CUDA framework, the Cell processor and, finally, how various architectures can be accessed in a distributed Grid environment. The main contribution of the paper, besides the parallelization approaches, is their systematic comparison regarding four important criteria: performance, programming comfort, accessibility, and cost-effectiveness. We report results of experiments on particular parallel machines of different architectures that confirm the findings of our systematic comparison. [ABSTRACT FROM AUTHOR]

With the parallel computer systems scaling-up, the measure index for performance of the systems demands a shift from traditional 'high performance' to 'high productivity.' This brings a new challenge to defining a synthetic, yet meaningful, measure index of multiple productivity variables; namely computing performance, reliability, energy consumption, parallel software development, etc. Traditional measures for large-scale parallel computer systems merely focus on computing performance, and are incapable of measuring the multiple productivity variables simultaneously in an effective manner. A recently proposed market-related money model, which pursues high utility/cost ratio, relies on money as a measure to consider the multiple productivity variables. Differing from the previous models, this paper proposes a novel system productivity speedup metric for large-scale parallel computer systems. The metric uses speedup instead of money to comprehensively unify the measures of multiple productivity variables. Finally, we propose a trade-off productivity measurement to weigh different productivity variables, to address different design targets. The measurement can facilitate the system evaluation, expose future technique tendencies, and guide future system design. [ABSTRACT FROM AUTHOR]

This paper presents a joint study of application and architecture to improve the performance and scalability of an irregular application-computing betweenness centrality-on a many-core architecture IBM Cyclops64. The characteristics of unstructured parallelism, dynamically non-contiguous memory access, and low arithmetic intensity in betweenness centrality pose an obstacle to an efficient mapping of parallel algorithms on such many-core architectures. By identifying several key architectural features, we propose and evaluate efficient strategies for achieving scalability on a massive multi-threading many-core architecture. We demonstrate several optimization strategies including multi-grain parallelism, just-in-time locality with explicit memory hierarchy and non-preemptive thread execution, and fine-grain data synchronization. Comparing with a conventional parallel algorithm, we get 4X-50X improvement in performance and 16X improvement in scalability on a 128-cores IBM Cyclops64 simulator. [ABSTRACT FROM AUTHOR]

The performance of memory and I/O systems is insufficient to catch up with that of COTS (Commercial Off-The-Shelf) CPU. PC clusters using COTS CPU have been employed for HPC. A cache-based processor is far less effective than a vector processor in applications with low spatial locality. Moreover, for HPC, Google-like server farms and database processing, insufficient capacity of main memory poses a serious problem. Power consumption of a Google-like server farm or a high-end HPC PC cluster is huge. In order to overcome these problems, we propose a concept of a memory and network enhancer equipped with scatter and gather vector access functions, high-performance network connectivity, and capacity extensibility. Communication mechanisms named LHS and LHC are also proposed. LHS and LHC are architectures for reducing latency for mixed messages with small controlling data and large data body. Examples of the killer applications of this new type of hardware are presented. This paper presents not only concepts and simulations but also real hardware prototypes named DIMMnet-2 and DIMMnet-3. This paper presents the evaluations concerning memory issues and network issues. We evaluate the module with NAS CG benchmark class C and Wisconsin benchmarks as applications with memory issues. Although evaluation for CG class C is difficult with conventional cycle-accurate simulation methods, we obtained the result for class C with our original method. As a result, we find that the module can improve its maximum performance about 25 times more with Wisconsin benchmarks. However, the results on a cache-based PC show the cache-line flushing degrades acceleration ratio. This shows the high potential of the proposed extended memory module and processors in combination with DMA-based main memory access such as SPU on Cell/B.E. that does not need cache-line flushing. The LHS and LHC communication mechanisms are evaluated in this paper. The evaluations of their effects on latency are shown. [ABSTRACT FROM AUTHOR]

In this paper, a new interconnection network called the incomplete crossed hypercube is proposed for connecting processors of parallel computing systems. The incomplete crossed hypercube architecture denoted by CI is made by combining two complete crossed hypercubes CQ n and CQ n− m for 1≤ m≤ n. Several topological properties of CI are analyzed. In particular, accurate mean internode distance formulas of both CQ n and CI are given. Compared with the incomplete enhanced hypercube EI, CI has shorter mean internode distance for large n. An optimal routing algorithm for CI is also described which guarantees the generation of a shortest path from a node to another in CI. [ABSTRACT FROM AUTHOR]

Distributed active storage architectures are designed to offload user-level processing to the peripheral from the host servers. In this paper, we report preliminary investigation on performance and fault recovery designs, as impacted by emerging storage interconnect protocols and state-of-the-art storage devices. Empirical results obtained using validated device-level and interconnect data demonstrate the significance of the said parameters on the overall system performance and reliability. [ABSTRACT FROM AUTHOR]

Research on peer-to-peer (P2P) networks has attracted much attention recently. A key factor is their ability to handle dynamics in the system in a distributed fashion, including ad hoc and dynamic join and departure of the peers and dynamic changes in the underlying network environment. As more and more innovating P2P applications appear, the need to support intuitive communication and synchronization among the peers in the P2P system becomes imperative. In this paper, we discuss how to build a tuple space on top of P2P systems and use on-line games as a target application. A simple API is supported for accessing the data stored in the tuple space and communicating between the peers. Through experiments and a demonstration game, we show that our system can facilitate the development of network games in a fully distributed environment. [ABSTRACT FROM AUTHOR]

Irregular array redistribution has been paid attention recently since it can distribute different size of data segment to heterogeneous processors according to their computational ability. It’s also the reason why it has been kept an eye on load balance. High Performance Fortran Version 2 (HPF2) provides GEN_BLOCK distribution format which facilitates generalized block distributions. In this paper, we present a two-phase degree-reduction ( TPDR) method for scheduling HPF2 irregular array redistribution. Using a bipartite communication graph, the first phase of TPDR schedules communication links adjacent to processors that with degree greater than two. A communication step will be scheduled follow each degree-reduction iteration. The second phase of TPDR schedules remaining messages of all processors that with degree-2 and degree-1 using an adjustable coloring mechanism. An extended algorithm based on TPDR is also presented in this paper. Effectiveness of the proposed methods not only avoids node contention but also shortens the overall communication cost. The proposed methods are also practicable due to low algorithmic complexity. To evaluate the performance of our methods, we have implemented both algorithms along with the divide-and-conquer algorithm and two scheduling mechanism. The simulation results show improvement of total communication costs. [ABSTRACT FROM AUTHOR]