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As CMOS technology approaches its physical and technical limits, alternative technologies such as nanotechnology or quantum computing are needed to overcome the challenges of lithography, transistor scaling, interconnects, and miniaturization. This article introduces a novel nanotechnology that uses atomic-scale silicon dangling bonds (ASDB) to create high-performance, low-power, nanoscale logic circuits. DBs are atoms that can form basic logic gates on a silicon surface using a scanning tunneling microscope device. ASDB can also be an alternative to the existing complementary metal oxide semiconductor (CMOS) technology. The article also proposes a new bar-shaped pattern to design gates and logic circuits with ASDB nano tecnolgoy. The bar-shaped pattern improves the reliability of the output, reduces the area and power consumption, and solves the problem of interatomic energy effects of ASDB. The article demonstrates the efficiency of the bar-shaped pattern by implementing two-input gates such as AND, NAND, OR, NOR, XOR, XNOR, and a 2:1 multiplexer with ASDB. The article also uses a powerful tool called SiQAD to simulate and verify the performance of the proposed structures with ASDB. According to the simulation results, the proposed logic gates are more energy efficient, stable, and compact than the previous structures. They consume 35% and 24.34% less energy and have 14.18% more stability, respectively. [ABSTRACT FROM AUTHOR]

A promising alternative for the CMOS technology is the Quantum-dot Cellular Automata (QCA) technology. In this technology, the low-latency, ultra-dense, and low-power consumption digital circuits are designed. Until now, many digital circuits are designed and improved in the QCA technology. The Arithmetic Logic Unit (ALU) is an important digital circuit that designed in this technology. The reversible logic gates such as NOT, Feynman, and Fredkin gates are important elements in the arithmetic circuits and processors design. In addition, considering the cell arrangements has a great influence on the area and speed of execution of computing devices in the QCA technology. This paper's goal is to build a new multilayer QCA Reversible ALU (RALU). In this paper, we used one HN and three Fredkin gates to design and implement a new and efficient RALU circuit in the QCA technology. The proposed QCA RALU circuit is simulated and tested using QCADesigner tool. The simulation results demonstrate that the developed QCA multilayer RALU has 489 cells, 0.36 µm2 area, 3.75 clock cycles delay, 2.02 meV average energy, and 5.41 nW power dissipation. In addition, the comparison indicates that the developed QCA RALU circuit has advantages compared to other QCA RALU circuits with regards to energy, area, latency, and cost. [ABSTRACT FROM AUTHOR]

Attribute-based encryption is a new cryptographic primitive that supports fine-grained access control of cloud data, and its access control function relies on the interaction of attributes and access structures. To achieve more flexible access control, attribute revocation has become an important problem that must be considered in the application process of attribute-based encryption. We propose and implement an efficient revocable ciphertext policy attribute-based encryption scheme based on the improvement of the scheme proposed by Tomida et al. Our scheme has the following characteristics: (1) It is adaptively secure under the Matrix Decisional Diffie–Hellman assumption; (2) it supports the multi-use of attribute classes and the negation of attribute values; (3) it supports the revocation of system attributes; and (4) the update of the key and ciphertext is completed by the trusted center and the cloud server, respectively, thereby decreasing revocation overhead for users. [ABSTRACT FROM AUTHOR]

Modern applications need to flexibly adjust the processing process according to the different environments and real-time processing, thus putting forward higher requirements for the reconfiguration performance of coarse-grained reconfigurable architecture (CGRA). Traditional dynamic reconfiguration requires constant configuration of the processor by the host computer. Still, this reconfiguration method severely restricts switching different tasks, making it difficult to achieve dynamic real-time reconfiguration and limiting performance improvement. This paper presents a real-time monitoring-based self-reconfiguration mechanism (RMSRM) based on the implementation of CGRA. This mechanism improves the reconfiguration performance by monitoring the execution process of the array in real-time through a programmable controller on the basis of the homogeneous processing element (PE) array and dynamic scheduling of PE array resources according to different application requirements. The proposed RMSRM is capable of feeding array execution state information to the programmable controller within 1 clock cycle, switching configurations between different tasks within 10 clock cycles, and shutting down the unnecessary PE/PEs according to the current configuration. To verify the correctness and efficiency, we model hardware with synthesizable RTL coding and implement it on FPGA and a chip. The experimental results show that RMSRM can effectively reduce the reconfiguration overhead compared with traditional reconfiguration methods. The volume of bits in the configuration file has decreased by an average of 39.37%, and the reconfiguration time has decreased by an average of 43.57%. Based on the SMIC 55nm process, the operating frequency can reach 320 MHz. Meanwhile, the resource consumption is 80506 logic gates, the chip area is 12 mm 2 , and the energy efficiency is 312 GOPS/W. [ABSTRACT FROM AUTHOR]

This work presents a novel approach to quantum computing by proposing a customizable hardware design of a dedicated processor that emulates the execution of quantum algorithms. Unlike software-based quantum computation simulators, which run on standard general-purpose computers and suffer from reduced performance, this hardware design, which is based on classical concepts of bits, registers and memories, aims to leverage pure parallelism and pipelined execution for efficient quantum computations via emulation. The architecture includes several key components: memories, computation unit, measurement unit and control unit. The quantum state memory stores the individual and group states of qubits. This memory is crucial for maintaining the quantum information required for quantum operations. Basic operators are stored in dedicated operator memory. Additionally, a scratch memory allows for larger operators to be dynamically built at runtime. The computation unit is responsible for performing complex number multiplications, which form the basis of tensor and matrix products necessary for executing quantum operations. A measurement unit enables quantum state sampling, which is an essential aspect of quantum computation. Furthermore, a control unit is incorporated to ensure the correct operation of the quantum processor's data path. It utilizes a microprogram to manage and coordinate the functional units. All the functional units communicate with each other through dedicated and shared data buses, depending on the frequency of information exchange. This enables efficient data transfer and coordination among the components. The proposed hardware design has been simulated and proved to be effective in executing quantum operations. By exploiting parallelism and employing a pipelined execution, this architecture overcomes the limitations of software-based simulators, delivering improved performance for emulating quantum algorithms. We use Grover's search algorithm as a benchmark to evaluate the performance of the proposed hardware design and compare it to software-based simulation and to hardware-based algorithm-dedicated emulation. [ABSTRACT FROM AUTHOR]

The arithmetic and logic unit (ALU) is a key element of complex circuits and an intrinsic part of the most widely recognized complex circuits in digital signal processing. Also, recent attention has been brought to reversible logic and quantum-dot cellular automata (QCA) because of their intrinsic capacity to decrease energy dissipation, which is a crucial need for low-power digital circuits. QCA will be the preferred technology for developing the subsequent generation of digital systems. These technologies played a substantial role in the design of the ALU for operations such as multiplication, subtraction, and division. In developing reversible logic and QCA technologies, the ALU is frequently studied as a central unit. Implementing an efficient ALU with low quantum cost and a small number of cells based on an efficient reversible block can solve all previous issues. Therefore, this research constructs a Feynman gate, a Fredkin gate, and full adder circuits using reversible logic and QCA technology. Using all of the specified circuits, a 20-operation ALU is constructed. The power consumption of the proposed ALU under various energy ranges demonstrated significant improvements over earlier designs. [ABSTRACT FROM AUTHOR]