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A P-layer can be formed on a SiC wafer surface by using multiple Al ion implantations and post- implantation annealing in a low pressure CVD reactor. The Al depth profile was almost box shaped with a height of 1 10 19 cm 3 and a depth of 550 nm. Three different annealing processes were developed to protect the wafer surface. Variations in RMS roughness have been measured and compared with each other. The implanted SiC, annealed with a carbon cap, maintains a high-quality surface with an RMS roughness as low as 3.8 nm. Macrosteps and terraces were found in the SiC surface, which annealed by the other two processes (protect in Ar/protect with SiC capped wafer in Ar). The RMS roughness is 12.2 nm and 6.6 nm, respectively.

High quality, homoepitaxial layers of 4H-SiC were grown on off-oriented 4H-SiC (0001) Si planes in a vertical low-pressure hot-wall CVD system (LPCVD) by using trichlorosilane (TCS) as a silicon precursor source together with ethylene (C2H4) as a carbon precursor source. The growth rate of 25–30 μm/h has been achieved at lower temperatures between 1500 and 1530 °C. The surface roughness and crystalline quality of 50 μm thick epitaxial layers (grown for 2 h) did not deteriorate compared with the corresponding results of thinner layers (grown for 30 min). The background doping concentration was reduced to 2.13 × 1015 cm−3. The effect of the C/Si ratio in the gas phase on growth rate and quality of the epi-layers was investigated.