1. Wafer bonding solution to epitaxial graphene–silicon integration
- Author
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Jan Kunc, Zelei Guo, Rui Dong, James Palmer, Walt A. de Heer, Claire Berger, Ming Ruan, John Hankinson, Yike Hu, Swapan K. Bhattacharya, School of Physics [Atlanta], Georgia Institute of Technology [Atlanta], Circuits électroniques quantiques Alpes (QuantECA), Institut Néel (NEEL), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)
- Subjects
Nanostructure ,Materials science ,Acoustics and Ultrasonics ,Silicon ,Wafer bonding ,Stacking ,FOS: Physical sciences ,Silicon on insulator ,chemistry.chemical_element ,02 engineering and technology ,01 natural sciences ,7. Clean energy ,law.invention ,Monocrystalline silicon ,law ,0103 physical sciences ,010302 applied physics ,Condensed Matter - Materials Science ,business.industry ,Graphene ,Materials Science (cond-mat.mtrl-sci) ,021001 nanoscience & nanotechnology ,Condensed Matter Physics ,Surfaces, Coatings and Films ,Electronic, Optical and Magnetic Materials ,chemistry ,[PHYS.COND.CM-MS]Physics [physics]/Condensed Matter [cond-mat]/Materials Science [cond-mat.mtrl-sci] ,Optoelectronics ,0210 nano-technology ,business ,Layer (electronics) - Abstract
The development of graphene electronics requires the integration of graphene devices with Si-CMOS technology. Most strategies involve the transfer of graphene sheets onto silicon, with the inherent difficulties of clean transfer and subsequent graphene nano-patterning that degrades considerably the electronic mobility of nanopatterned graphene. Epitaxial graphene (EG) by contrast is grown on an essentially perfect crystalline (semi-insulating) surface, and graphene nanostructures with exceptional properties have been realized by a selective growth process on tailored SiC surface that requires no graphene patterning. However, the temperatures required in this structured growth process are too high for silicon technology. Here we demonstrate a new graphene to Si integration strategy, with a bonded and interconnected compact double-wafer structure. Using silicon-on-insulator technology (SOI) a thin monocrystalline silicon layer ready for CMOS processing is applied on top of epitaxial graphene on SiC. The parallel Si and graphene platforms are interconnected by metal vias. This method inspired by the industrial development of 3d hyper-integration stacking thin-film electronic devices preserves the advantages of epitaxial graphene and enables the full spectrum of CMOS processing., 15 pages, 7 figures
- Published
- 2014