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Background: As semiconductor technologies continue to shrink, optical proximity correction may not have enough space to optimize layout due to limitations from adjacent layers. Lithography friendly design (LFD) becomes a powerful tool to detect potential lithography yield killers for fabless side from 14-nm technology node and beyond. Design layout can be modified before tape-out to avoid future rework. However, huge runtime is the bottleneck of LFD. Aim: Our paper puts forward an innovative layout decomposing algorithm to accelerate LFD at full-chip level. Approach: The proposed projection-based high coverage fast (PBHCF) LFD layout decomposing algorithm partitions the full-chip layout as a set of unique patterns. The simulation runtime can be reduced by only simulating every unique pattern and corresponding optical interaction range in full chip. The LFD hotspots will be classified, analyzed, and repaired by pattern matching in batches for full-chip layout. Results: The experiments compare hotspot accuracies and prediction speeds of proposed PBHCF LFD and the most commonly used accelerated algorithm, Smart LFD, for different layouts at chip level for metal 2 layer of 12-nm technology node with pure unidirectional routings. On one hand, the average accuracy of PBHCF LFD can achieve 97.07%, improving 3.4% than Smart LFD on average. On the other hand, PBHCF LFD improves the average prediction speed over regular LFD 19.51%. And the PBHCF LFD is faster than Smart LFD by 5.96%. Conclusions: PBHCF LFD achieves higher accuracy and less runtime than Smart LFD. The verification experiments conducted on layouts at chip level show the feasibility of the proposed methodology. [ABSTRACT FROM AUTHOR]

Background: As semiconductor technologies continue to shrink, the growth in the number of process variables and combined effects tighten the overall process window, which leads to a more serious yield loss. Yield cannot be totally guaranteed by design rule check and verifications of optical proximity correction, due to complex process variations. The joint effects from unreasonable designs and unstable control of critical dimensions and overlay mainly contribute to the formation of bridging defects in critical interconnect layers. Aim: Our paper puts forward a model to detect the potential bridging region and predicts the corresponding failure probability under a litho-etch-litho-etch process. Approach: The proposed model is based on input error sources from variations of lithography and etch processes. In this scheme, bridging is expected when the minimum space of simulated postetch contours within a specific range is smaller than a user-defined bridging threshold. Gaussian distribution characteristics of line edge roughness (LER) and overlay are considered in the proposed model. Moreover, the proposed model provides meaningful guidelines for bridging prediction with the use of process variation bands. Results: The experiment results indicate consistency and validity of theoretical derivation of the proposed model. The concrete impacts of LER and overlay on the model have been quantitatively analyzed as well. Conclusions: According to the predicted probabilities, the model can early discover potential bridging defects quantitatively by considering the statistical properties of process variations with very few calculations and can give a ranking of failure severity as a decision foundation for design rule optimization. [ABSTRACT FROM AUTHOR]

Hotspot detection focused on lithography induced defects becomes crucial at advanced node due to the increasing complexity of the design and manufacture process. Compared with traditional lithography simulation techniques for hotspot detection, machine-learning-based methods have shown significant advantages attributing to the efficiency and generality of their model. However, most convolutional neural network-based hotspot detector can only inference a layout pattern at once. Therefore, sampling clip patterns from the detected layout is the bottleneck of the whole process and determines the performance of hotspot detection. We designed a flow to generate filter rules by clustering analysis of known hotspots, which can efficiently extract layout clips as detected samples to hotspot classifier. We further propose a feature parametric optimization method to extract valuable graphic features for classifiers and reduce redundancy from context patterns. Experimental results demonstrate that these techniques improve the accuracy of hotspots detection. [ABSTRACT FROM AUTHOR]

Background: In datasets for hotspot detection in physical verification, data are predominantly composed of non-hotspot samples with only a small percentage of hotspot ones; this leads to the class imbalance problem, which usually hinders the performance of classifiers. Aim: We aim to enrich datasets by applying a data augmentation technique. Approach: We propose a data augmentation flow-based generative adversarial network (GAN) to generate high-resolution hotspot samples. Results: We evaluated our flow with the current state-of-the-art convolutional neural network hotspot classifier by comparison with conventional data augmentation techniques. Experimental results demonstrate that the accuracy improvement of our work can reach 3% at the same false alarm rate and the false alarm rate reduction can reach 5% at the same accuracy. Conclusions: Our study demonstrates that rational hotspot classification can improve the efficiency of data. It also highlights the potential of GAN to generate complicated layout patterns. [ABSTRACT FROM AUTHOR]